Device & Host Support
This release supports the following Altera® device families:
- Stratix® II (Verified in hardware for the first time with this release)
- Cyclone™
- Stratix
This release supports the following host environments:
- Quartus® II 4.1 SP1 and later
- Windows XP, Windows 2000, Windows NT 4.0, & ModelSim version 5.8c OEM in conjunction with the precompiled libraries for Quartus II 4.1 SP1.
SOPC Builder and Quartus II Software Support
This section documents changes related to SOPC Builder and Quartus II software.
JTAG Identification Conflicts (SPR 157902)
A mechanism was added to ensure unique Joint Test Action Group (JTAG) identifications for each system module in Quartus II projects with multiple SOPC Builder system modules.
Interface Can Not Read Verilog "define" Files (SPR 128922)
The interface to user logic can not read verilog files that use the term "define."
Multiple CPUs With Same Reset Address (SPR 154954)
The Nios® II processor version 1.0 did not allow generation of a system with two or more processors with the same reset address or exception vector. This is now possible in version 1.01.
ModelSim Simulation (SPR 159557)
Nios II processor v1.01 simulation using ModelSim® 6.0 (SE, PE, or Altera Editions) has not been fully validated and may result in fatal errors during simulation. ModelSim 5.8c Altera Edition, and 5.8a SE and PE are fully supported.
If you attempt to use ModelSim Altera version 5.7e without installing the Quartus II 4.0 SP1 precompiled libraries, you must delete your <system_name>_sim directory under your Quartus II project directory and regenerate your SOPC Builder system. This ensures that the appropriate ModelSim .ini file is created for the simulation.
Peripheral Support
This section documents changes to the hardware peripherals included in the Nios II Development Kit.
Interface Revision to SDRAM Controller With Avalon® Bus (SPR 157864)
To correct a problem with incorrect data results during reads from SDRAM with CAS latency set to 3, the SDRAM controller now always drives all DQM pins to their inactive level (enabling SDRAM DQ pin drivers) during reads.
JTAG UARTs Not Supported by Legacy SDK Flow (SPR 145610)
The JTAG universal asynchronous receiver/transmitter (UART) did not exist before the release of the Nios II processor, and therefore the pre-Nios II legacy SDK flow provides no driver for the JTAG UART.
