FPGA, CPLD, and ASIC solutions from Altera
  • Download Center
  • Literature
Sign in/register
myAltera Account
Welcome
  •   myAltera
  •   Logout
  • Products
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design & Support Services
    • Literature
  • End Markets
    • Automotive
    • Broadcast
    • Computer & Storage
    • Consumer
    • Industrial
    • Medical
    • Military
    • Test & Measurement
    • Wireless
    • Wireline
  • Technology
    • DSP
    • External Memory
    • Embedded Processing
    • Transceivers
    • Parallel I/O
    • Signal Integrity
    • System Integration
  • Training
    • Training Courses
    • University Program
    • Webcasts & Videos
    • Demonstrations
    • Events Calendar
  • Support
    • Design & Support Resources
    • Knowledge Database
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design Examples
    • Downloads
    • User Communities/Forums
    • mySupport
  • About Altera
    • About Us
    • Environmental
    • Customer Successes
    • Partners
    • Newsroom
    • Investor Relations
    • Jobs
    • Contact Us
  • Buy Online
    • Devices
    • Design Software
    • Development & Education Kits
    • Cables & Programming Hardware
    • Intellectual Property
  • Entire Site
  • Part Number
  • Knowledge Database
  • Support & Technical Docs
  • Forums & Wiki
Username:  
Password:  
 
Forgot my username or password
Don't have myAltera account? Register Now.
Enter your email address:

Nios II Embedded Design Suite Release Notes

Home > Support > Intellectual Property > Nios II Embedded Design Suite > Release Notes

Release and errata information for the Nios® II processor core are included in the MegaCore® Intellectual Property (IP) Library release notes and errata. Release and errata information for the Nios II Embedded Design Suite (EDS), including new features, bug fixes, enhancements, known issues in the tools, peripherals, and example designs, are in the Nios II EDS Release Notes and Errata. For a complete list of release notes and errata for all Altera® products, visit the Release Notes and Errata page.

  • MegaCore IP Library Release Notes and Errata (PDF)
  • Nios II EDS Release Notes and Errata (PDF) includes information on releases from the past year

Release Note Archives

  • Version 7.1 Release Notes (PDF)
  • Version 7.0 Release Notes (PDF)
  • Version 6.1 Release Notes (PDF)
  • Version 6.0 Service Pack 1 (SP1) Release Notes (PDF)
  • Version 6.0 Release Notes (PDF)
  • Version 5.1 Service Pack 1 (SP1) Release Notes (PDF)
  • Version 5.1 Release Notes (PDF)
  • Version 5.0.1 Release Notes (PDF)
  • Version 5.0 Release Notes
  • Version 1.1 Release Notes 
  • Version 1.01 Release Notes

For revision history of the Nios II processor hardware, see the Nios II Processor Revision History chapter of the
Nios II Processor Reference Handbook (PDF).

Rate This Page


  • Embedded Processors
    • Nios II Embedded Design Suite
      • Release Notes
      • Errata Sheets
      • Software Development
      • Literature
    • Nios II Development Kits
  • DSP
    • Overview
    • DSP Builder
    • IP Cores
    • Development Kits
  • Interface Protocols
    • PCI Express
    • POS-PHY Level 4
    • SDI
    • Triple Speed Ethernet
    • 10-Gbps Ethernet
    • RapidIO
    Please give us feedback
    Products | End Markets | Technology | Training | Support | About Altera | Buy Online
    Jobs | Investor Relations | Contact Us | Site Map | Privacy | Legal Notice
    Copyright © 1995-2010 Altera Corporation. All Rights Reserved.
    Altera Forum
    Altera
    Forum
    Twitter
    Twitter
    RSS
    RSS
    Facebook
    Facebook
    Flickr
    Flickr
    YouTube
    YouTube
    Email Updates
    Email
    Updates