| 1 |
| The Quartus® II compiler fails for Stratix II GX designs with transceivers configured in bonded x4 (PCI Express (PIPE) x4, XAUI and Basic x4) and bonded x8 (PCI Express (PIPE) x8) configurations depending on channel placement. Are there any channel placement constraints in these configurations?
Is there any recommendation for lane mapping between the Stratix II GX transceiver physical channels to the PCI Express edge connector?
Quartus® II software requires specific channel placements for the following bonded channel configurations to compile the design succesfully.
1) x4 Bonded Channel…
www.altera.com/support/kdb/solutions/rd05072008_61.html - 2008-05-08 |
| 2 |
| Are 25-Ω series resistors required in Cyclone III active parallel (AP) configuration mode when using the Intel Flash at 2.5V/3.0V/3.3V I/O standard?
No, for there is no series resistors requirement on the flash pins. According to Intel’s P30 IBIS model, the output buffer will not overshoot above 4.1V. Thus, series re…
www.altera.com/support/kdb/solutions/rd03162007_767.html - 2008-05-06 |
| 3 |
| Are the final numbers available for Cyclone III Uncompressed Raw Binary File (RBF) Sizes?
Yes, the final RBF numbers are below and will be updated in the next revision of the Cyclone® III Handbook.
EP3C5/EP3C10 = 2,949,120 bits ~ 3.0 MbitsEP3C16 = 4,087,808 b…
www.altera.com/support/kdb/solutions/rd04292008_403.html - 2008-05-06 |
| 4 |
| Can I directly connect (DC couple) a 3.3V LVDS buffer to a 2.5V LVDS buffer?
Yes, when working with the LVDS I/O standard, the LVDS signaling properties of the buffer should be your focus, not the power source of the buffer. As long as the commo…
www.altera.com/support/kdb/solutions/rd01242007_248.html - 2008-05-06 |
| 5 |
| Can I perform Boundary Scan and / or use the SignalTap II logic analyzer after my Stratix II device has been programmed with the Advanced Encryption Standard (AES) security key?
Yes you can still perform Boundary Scan testing and / or use the SignalTap® II logic analyzer to analyze functional data within the FPGA. However, JTAG configuration is n…
www.altera.com/support/kdb/solutions/rd02282007_910.html - 2008-05-06 |
| 6 |
| Can I use the external PLL option when implementing the altlvds megafunction with a deserialization factor of 2?
No, when you have a deserialization factor of 2, the SERDES is bypassed and the functionality is implemented in double data rate (DDR) registers. You need at least a…
www.altera.com/support/kdb/solutions/rd01262007_740.html - 2008-05-06 |
| 7 |
| Does the Cyclone II Early Power Estimator (EPE) take into account the power dissipated in the external resistor network required to implement LVDS outputs in Cyclone II devices, when estimating LVDS I/O Power?
Yes, the Cyclone® II EPE LVDS power model does account for the external resistor network into the power estimation consideration.
www.altera.com/support/kdb/solutions/rd01262007_997.html - 2008-05-06 |
| 8 |
| Error: Kernel mode driver not installed
You receive this error message if you do not have programming hardware drivers set up in the Quartus® II software. To set up drivers, follow instructions for the appropriate driver…
www.altera.com/support/kdb/solutions/rd03282007_532.html - 2008-05-06 |
| 9 |
| Is the internal configuration oscillator in Cyclone® III devices turned off once the device enters user mode?
By default, the configuration oscillator is disabled once configuration and initialization is complete and the device has entered user mode.
However, if user mode CRC …
www.altera.com/support/kdb/solutions/rd03302007_390.html - 2008-05-06 |
| 10 |
| Why am I unable to sample pins that are configured as outputs when performing Boundary Scan testing on my programmed MAX® II device?
By default, the input buffers are turned off for I/O pins that are configured as outputs in your design.
To regenerate your programming file to enable the input buffers, you need …
www.altera.com/support/kdb/solutions/rd03282007_450.html - 2008-05-06 |
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