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| 1 | Why do I get build error "SEVERE: java.lang.RuntimeException: Error in Tcl script C:\altera\72\ip\nios2_ip\altera_nios2\altera_nios2_hal_sw.tcl" Quartus® II keeps a cache folder of older version components in C:\Documents and Settings\<username>\.altera.quartus\ip\9.1\ip_search_path\user_components.ipx. Delete this ca… www.altera.com/support/kdb/solutions/rd02182010_732.html - 2010-03-19 |
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| 2 | Can I implement both of the Altera Serial FlashLoader and altasmi_parallel megafunction in the same design when using Quartus II software? Starting from Quartus® II software version 8.1, you are not allowed to have both Serial FlashLoader and altasmi_parallel megafunction in the same design. This is because both megaf… www.altera.com/support/kdb/solutions/rd01112010_771.html - 2010-03-18 |
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| 3 | How do I set the Cyclone III or Cyclone IV E device I/O pins to tri-state the Active Parallel (AP) configuration bus for an external master device to take control of the bus? For another master to take control of the AP configuration bus, the master must assert nCONFIG low for at least 500 ns to reset the Cyclone® III or Cyclone IV E device and de-asser… www.altera.com/support/kdb/solutions/rd03092010_524.html - 2010-03-18 |
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| 4 | I have link training or down training hardware issues in my PCI Express Compiler Stratix IV GX HIP Gen2 x4 or x8 in Quartus 9.1 SP1. If you are experiencing problems with link training or down training in Altera® Stratix® IV devices using the Altera PCI Express Compiler targeting the hardware IP block (HI… www.altera.com/support/kdb/solutions/rd03012010_867.html - 2010-03-18 |
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| 5 | Warning: Ignored assignment: set_false_path -from [get_pins -compatibility_mode {*_alt_mem_phy_inst|*mmc|mimic_done_out*}] -to [get_keepers {*_alt_mem_phy_inst|*seq_wrapper|*seq_inst|*dgrb|*v_mmc_seq_done_1r}] This warning may be seen in the Quartus® II software version 9.1 SP1 when your design instantiates DDR3 High Performance Controller MegaCore® with leveling. You can safely ignore t… www.altera.com/support/kdb/solutions/rd03052010_717.html - 2010-03-18 |
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| 6 | What is different between Dynamic ODT and Dynamic OCT when interfacing DDR3 SDRAM with Stratix III or Stratix IV FPGAs? Dynamic On Die Termination (ODT) Dynamic ODT is a new feature on DDR3 SDRAM memories and not available in DDR2 SDRAM memories. Dynamic ODT provides systems with increased flexibi… www.altera.com/support/kdb/solutions/rd02192010_508.html - 2010-03-18 |
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| 7 | What is the actual uncompressed .rbf file size for Cyclone III LS devices? The .rbf sizes for Cyclone® III LS devices published in the Cyclone III device handbook are the preliminary numbers based on estimation. The actual .rbf sizes generated beginning w… www.altera.com/support/kdb/solutions/rd03142010_789.html - 2010-03-18 |
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| 8 | Does the PowerPlay Power Analyzer detect IP (for example encrypted IP)? Yes, the Power PlayPower Analyzer detects IP. However some power analysis schemes require fully-licensed IP to enable simulation in third-party tools. For more i… www.altera.com/support/kdb/solutions/rd12302009_523.html - 2010-03-16 |
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| 9 | Error: Cannot start the command line quartus_map You may see this error in the Quartus® II software version 9.1 SP1, when Parallel Synthesis is enabled and multiple processors are allowed during compilation. The Quartus II s… www.altera.com/support/kdb/solutions/rd03072010_338.html - 2010-03-16 |
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| 10 | Fatal: (vsim-3421) Value -1 is out of range 0 to 2147483647 You may see this error in the Quartus® II software version 9.1 SP1 and earlier, during simulation of Arria II GX designs containing ALTLDVS IP. The error may occur when you specify… www.altera.com/support/kdb/solutions/rd03112010_988.html - 2010-03-16 |
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