| Known issues for Arria GX |
| Results 1 - 5 of about 5. |
| 1 | Arria GX Device Handbook: Known Issues Issue 10003010, Volume 1, Chapter 2 "Arria GX Architecture" Version 1.3 Note 3 in table 2-25 states the following for the LVDS VCCIO requirements: "VCCIO is 3.3 V when using… www.altera.com/support/kdb/solutions/rd09232008_841.html - 2009-05-29 |
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| 2 | What is the minimum number of DLL clock cycles required during an SDRAM refresh cycle for Stratix, Stratix GX, Stratix II, Stratix II GX, HardCopy, HardCopy II and Arria GX devices? If the DLL reference clock is stopped and restarted thereafter, such as during an SDRAM refresh cycle, a minimum of 16 clock cycles is needed before data can be captured properly… www.altera.com/support/kdb/solutions/rd11292007_918.html - 2009-03-19 |
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| 3 | Is the on-chip biasing network of the REFCLK input pin in Altera transceiver based devices enabled before or during device configuration? No, the on-chip biasing network of the REFCLK input pin is disabled before and during device configuration in the Altera® transceiver based products such as S… www.altera.com/support/kdb/solutions/rd01262009_423.html - 2009-03-04 |
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| 4 | Error: Pin You may see this error because the Quartus® II software versions 7.2 and earlier incorrectly allows you to make series 25 or 50 ohm on-chip termination (OCT) with ca… www.altera.com/support/kdb/solutions/rd03052008_418.html - 2008-07-22 |
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| 5 | Error: Pin Arria®GX devices do not support OCT with calibration. If you make this assignment to any pins of an ArriaGX device, the Quartus® II design software will issue this error mess… www.altera.com/support/kdb/solutions/rd03182008_736.html - 2008-05-13 |
