| Known issues for Cyclone III |
| Results 1 - 10 of about 10. |
| 1 | Why is the output voltage signal not monotonic at the rising and falling edges of the 1.8V SSTL 50 ohm On-Chip Termination (OCT) without calibration IBIS models in Cyclone III devices? There is a known issue with the final Cyclone® III device IBIS models where the output voltage signal is not monotonic at the rising and falling edges of the 1.8V SSTL 50 ohm … www.altera.com/support/kdb/solutions/rd08272009_152.html - 2010-06-30 |
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| 2 | Can I merge PLLs when cascading post-scale counters in Cyclone III and Cyclone IV devices using Quartus II software version 9.1? For Cyclone® III and Cyclone IV devices, the Quartus® II 9.1 software will generate the wrong low frequency output clocks if the following two conditions occur at the same time: (… www.altera.com/support/kdb/solutions/rd01262010_869.html - 2010-01-28 |
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| 3 | Why does Active Serial Configuration of a Stratix III or Cyclone III LS device fail when I use an uncompressed configuration file? You may experience configuration failure with an uncompressed file due to CONF_DONE rising too early in Stratix® III or Cyclone® III LS devices during Active Serial (AS) con… www.altera.com/support/kdb/solutions/rd08062009_90.html - 2009-11-09 |
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| 4 | Cyclone III Device Handbook: Known Issues Issue 10006410: Volumn 1, Chapter 9 “Configuration, Design Security, and Remote System Upgrades in Cyclone III Devices” version 1.2 The current stated specification for tS… www.altera.com/support/kdb/solutions/rd02252008_304.html - 2009-09-10 |
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| 5 | Why do I see glitches on the output port of a clock control block in Cyclone III devices when I have ensure glitch free switchover enabled? There is a bug in Quartus® II software which affects the "ensure glitch-free switchover implementation" in the Cyclone® III device altclkcntrl megafunction. If you select this opti… www.altera.com/support/kdb/solutions/rd09082009_706.html - 2009-09-08 |
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| 6 | Why does my Cyclone III FPGA fail to access the EPCS device using the EPCS Controller module? In Cyclone® III devices, the EPCS controller does not automatically assign its output pins to the dedicated configuration pins on the FPGA. Instead, the output pins are exported to… www.altera.com/support/kdb/solutions/rd11012007_792.html - 2009-08-26 |
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| 7 | Are there any known issues with the Cyclone III Early Power Estimator (EPE) version 8.0 with regards to clock power estimation? Yes, version 8.0 of the Cyclone® III EPE incorrectly over estimates the clock power for the EP3C16 and EP3C55 devices. This is fixed in the version 8.0.1 of the EPE. www.altera.com/support/kdb/solutions/rd06092008_217.html - 2008-06-17 |
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| 8 | Is there any known issue with the DCLK slew rate setting for Cyclone III devices in Quartus II software version 7.1? Yes, there is a problem with the DCLK slew rate setting for Cyclone® III devices in Quartus® II software version 7.1. The software incorrectly sets a slower DCLK slew rate in user … www.altera.com/support/kdb/solutions/rd05302007_828.html - 2007-06-08 |
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| 9 | Are there any known issues with Cyclone® III Device Handbook version 1.0, Chapter 9 External Memory Interfaces in Cyclone III Devices? There is an error in Table 9-4 Cyclone III DQS and DQ Bus Mode Support for Each Side of the device. Note (4) that mentions no DM pin support for the DQS/DQ groups at the top a… www.altera.com/support/kdb/solutions/rd05022007_27.html - 2007-05-15 |
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| 10 | Are there any known issues with the DDR & DDR2 High-Performance Controller MegaCore function or the ALTMEMPHY megafunction that can cause hardware failures? Yes, there is a problem with the DDR & DDR2 High-Performance Controller MegaCore® function versions 6.1 & 7.0, and the ALTMEMPHY megafunction in the Quartus® II software … www.altera.com/support/kdb/solutions/rd03092007_117.html - 2007-03-20 |
