| Known issues for Stratix II GX |
| Results 1 - 10 of about 30. |
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| 1 | Are there any known issues forcing the 8b10b disparity through channel interface? Yes. When ‘Channel Interface’ option is enabled, forcing the 8b/10b disparity through the tx_datainfull[] port does not work. All transceiver designs using ‘Channel Interface’… www.altera.com/support/kdb/solutions/rd09232009_29.html - 2009-09-28 |
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| 2 | Why does the ALT2GXB MegaWizard Plug-In Manager display the message "MegaWizard initializing: please wait" and remain disabled? This behavior occurs due to a problem in the MegaWizard® Plug-In Manager when you select the ALT2GXB megafunction for Stratix® II GX or Arria® GX devices in the Quartus®&… www.altera.com/support/kdb/solutions/rd02112009_555.html - 2009-06-09 |
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| 3 | Why can't I get the SDI demonstration design that is shipped with the Stratix® II GX Audio/ Video development kit to function as described in the "Audio-Video Development Kit
Stratix II GX Edition Getting Started User Guide"? The "Audio-Video Development Kit Stratix II GX Edition Getting Started User Guide" that comes with the Stratix II GX Audio/Video development kit is out of date. For details o… www.altera.com/support/kdb/solutions/rd10212008_803.html - 2009-05-12 |
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| 4 | What is the minimum number of DLL clock cycles required during an SDRAM refresh cycle for Stratix, Stratix GX, Stratix II, Stratix II GX, HardCopy, HardCopy II and Arria GX devices? If the DLL reference clock is stopped and restarted thereafter, such as during an SDRAM refresh cycle, a minimum of 16 clock cycles is needed before data can be captured properly… www.altera.com/support/kdb/solutions/rd11292007_918.html - 2009-03-19 |
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| 5 | Is the on-chip biasing network of the REFCLK input pin in Altera transceiver based devices enabled before or during device configuration? No, the on-chip biasing network of the REFCLK input pin is disabled before and during device configuration in the Altera® transceiver based products such as S… www.altera.com/support/kdb/solutions/rd01262009_423.html - 2009-03-04 |
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| 6 | What are the proper MSEL and VCCSEL configuration settings for Stratix II devices when VCCIO for I/O bank 3 is less than 2.5V? For boards designed with Stratix® II to power-up and configure correctly there are four cases to consider based on the Power On Reset (POR) trip point and … www.altera.com/support/kdb/solutions/rd06172005_556.html - 2009-01-28 |
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| 7 | How do I interface with the EPCS serial configuration device which requires 3.3V if the VCCIO of the bank in which my configuration pins resides is set to 1.8V for Stratix II and Stratix II GX devices? For Stratix® II and Stratix II GX devices, when the VCCIO level of the bank in which your configuration pins reside is set to 1.8V and you wish to interface with an EPCS serial con… www.altera.com/support/kdb/solutions/rd05032006_972.html - 2008-11-05 |
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| 8 | Can the Stratix II GX transceiver Word Aligner be bypassed ? The Stratix® II GX Word Aligner cannot be bypassed and must be used. However, you can use the rx_enapatternalign port to set the word alignment to not align to the patte… www.altera.com/support/kdb/solutions/rd10242007_620.html - 2008-05-28 |
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| 9 | How do I set 6dB equalizer DC gain in ALT2GXB MegaWizard? The equalizer DC gain selections in Quartus® II software version 7.2 or earlier Megawizard are 0 (0dB), 1 (3dB) and 2 (3dB). To set 6dB equalizer DC gain, m… www.altera.com/support/kdb/solutions/rd11142007_393.html - 2008-05-28 |
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| 10 | The Quartus® II compiler fails for Stratix II GX designs with transceivers configured in bonded x4 (PCI Express (PIPE) x4, XAUI and Basic x4) and bonded x8 (PCI Express (PIPE) x8) configurations depending on channel placement. Are there any channel placement constraints in these configurations?
Is there any recommendation for lane mapping between the Stratix II GX transceiver physical channels to the PCI Express edge connector? Quartus® II software requires specific channel placements for the following bonded channel configurations to compile the design succesfully. 1) x4 Bonded Channel… www.altera.com/support/kdb/solutions/rd05072008_61.html - 2008-05-08 |
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