Solution ID: 1294
Last Modified: Feb 01, 2006
Product Category: Devices
Product Area: Configuration
Product Sub-area: Configuration I/O

Problem

What does the 100-ms power-on-reset time for configuration EPROM devices refer to?

Solution

The power-on-reset time, approximated at 100 ms in the Configuration Devices Data Sheet, refers to the maximum time that occurs from when the power is turned on until the low-to-high transition is seen on the output enable OE input and nSTATUS pin.

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