Solution ID: rd01312005_402
Last Modified: Jan 08, 2008
Product Category: Design Software
Product Area: On-Chip Debug
Product Sub-area: SignalTap II
Device Family: STRATIX II
Title
Why does the SignalTap<SUP>®</SUP> II logic analyzer display incorrect data when the acquisition buffer is in Stratix<SUP>®</SUP> II M-RAM blocks?
Description
The SignalTap II logic analyzer may display corrupted data for Stratix II devices when the acquisition buffer is implemented in M-RAM blocks with the Quartus II software versions 4.1, 4.2, and 4.2 SP1 due to an issue with Stratix II M-RAMs as described in the Stratix II FPGA Family Errata Sheet.This problem is fixed in the Quartus II software beginning with version 5.0 because the acquisition buffer is not implemented in M-RAM blocks.
In the Quartus II software version 4.1, 4.2, and 4.2 SP1, you can change the RAM type to M4K or M512 blocks in the SignalTap File (.stp) to implement the acquisition buffer outside of M-RAM blocks.
Alternately, you can also install a patch for the Quartus II software version 4.2 SP1. Contact Altera® Applications for patch 1.13. Patch 0.13 is also available for the Quartus II software version 4.2, but Altera recommends upgrading to SP1 and then obtaining patch 1.13.
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