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Solution ID: rd02282007_910
Last Modified: May 06, 2008
Product Category: Devices
Product Area: Configuration
Product Sub-area: Design Security/AES
Problem
Can I perform Boundary Scan and / or use the SignalTap II logic analyzer after my Stratix II device has been programmed with the Advanced Encryption Standard (AES) security key?
Solution
Yes you can still perform Boundary Scan testing and / or use the SignalTap® II logic analyzer to analyze functional data within the FPGA. However, JTAG configuration is not possible after the security key has been programmed into the Stratix® II FPGA.
When using the SignalTap II logic analyzer, you must first configure the device with an encrypted configuration file using Passive Serial (PS), Fast Passive Parallel (FPP) or Active Serial (AS) configuration modes. The design must contain at least one instance of the SignalTap II logic analyzer. Once the FPGA is configured with a SignalTap II logic analyzer instance in the design, then when you open the SignalTap II logic analyzer window/GUI in the Quartus® II software, you simply need to scan the chain and it will be ready to acquire data over JTAG.
Feedback
Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
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