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Solution ID: rd03062006_72
Last Modified: Mar 22, 2006
Product Category: Design Software
Product Area: Synthesis
Product Sub-area: Other
Problem
Why does my design fail to simulate or function correctly on my board but pass when I delete the db directory and recompile the design in the Quartus II software version 5.1, 5.1 SP1 and 5.1 SP2?
Solution
Due to a problem in versions 5.1, 5.1 SP1 and 5.1 SP2 of the QuartusII® software, a functional failure may occur in designs with either of the following characteristics:
- The design contains inferred ROM. A design with inferred ROM has the following Information messages in the Analysis & Synthesis Messages :
Info: Inferred <number> megafunctions from design logic
Info: Inferred altsyncram megafunction (OPERATION_MODE=ROM, …) from the following design logic: <logic name>
- The path for the memory initialization file of any RAM or ROM is specified through User Library paths. RAM or ROM instantiations that specify absolute paths to memory initialization files, or with memory initialization files in the project directory, are not affected.
The issue occurs when changes to RAM and ROM memory initialization files are not recognized properly in a subsequent compilation. This can cause the design to fail functionally in a gate-level timing simulation or hardware after a successful compilation.
The issue is caused by a failure to detect changes to the memory contents of ROM inferred by the Quartus II software, or changes to the memory initialization files of an instantiated RAM or ROM. The Quartus II software versions 5.0 and earlier do not have this issue.
To fix this issue, install the patch listed below for your version of the Quartus II software.
You can work around this issue, without a patch,by deleting the db subdirectory in your project directory before every compilation.
Feedback
Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
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