Solution ID: rd03092010_524
Last Modified: Mar 18, 2010
Product Category: Devices
Product Area: Configuration (FPGA)
Product Sub-area: Active Parallel (AP)
Device Family: CYCLONE IV E
Title
How do I set the Cyclone III or Cyclone IV E device I/O pins to tri-state the Active Parallel (AP) configuration bus for an external master device to take control of the bus?
Description
For another master to take control of the AP configuration bus, the master must assert nCONFIG low for at least 500 ns to reset the Cyclone® III or Cyclone IV E device and de-assert the nCE high to disable the Cyclone III or Cyclone IV E device. This resets the Cyclone III or Cyclone IV E device and causes it to tri-state its AP configuration bus. The other master then takes control of the AP configuration bus.
After the other master device is done, it releases the AP configuration bus, then releases the nCE pin, and finally pulses nCONFIG low to restart the configuration. In the AP configuration scheme, multiple masters share the parallel flash and the bus control is negotiated by the nCE pin.
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