Solution ID: rd03252011_985
Last Modified: Jun 28, 2011
Product Category: Intellectual Property
Product Area: Comm, Interface & Peripherals
Product Sub-area: Core Behavior / Operation
Software: Quartus II PC
IP Product: Triple Speed Ethernet MAC
Title
Why don't reset_rx_clk and reset_tx_clk signals of PCS only variant and PCS plus PMA varinat of Triple Speed Ethernet IP MegaCore synchronize to rx_clk and tx_clk?
Description
The following patch provides a solution to ensure reset_rx_clk signal is synchronized to rx_clk and reset_tx_clk signal is synchronized to tx_clk.
Please download the appropriate Quartus® II software version 10.1SP1 patch 1.77 from the following links:
Quartus II software version 10.1SP1 patch 1.77 for Windows
Quartus II software version 10.1SP1 patch 1.77 for Linux
Quartus II software version 10.1SP1 ReadMe for patch 1.77
Caution:
You must either have previously installed the Quartus II 10.1 SP1 software or must install the Quartus II 10.1 SP1 software before installing this patch. Otherwise, the patch will not be installed correctly and the Quartus II software will not run properly.
After you install the patch please regenerate your Triple Speed Ethernet MegaCore® before you compile your design.
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Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
