Solution ID: rd05212009_315
Last Modified: Nov 21, 2010
Product Category: Intellectual Property
Product Area: Other (Intellectual Property)
Product Sub-area: Other (IP)
Software: N/A
Device Family: N/A
IP Product: SDI Video Interface
Title
How is the FIFO being used during the transfer of rx_data from the RX SDI MegaCore to tx_data of the TX SDI MegaCore?
Description
In the Altera® SDI MegaCore® Function the FIFO is used between the receive clock domain logic and the transmit clock domain logic. The FIFO wrclk is connected to rx_clk. The user can write the rx_data into the FIFO when rx_data_valid_out is asserted.
The TX SDI MegaCore function requires the reference clock (tx_serial_refclk) to generate gxb_tx_clkout. The FIFO rdclk is connected to gxb_tx_clkout.
The tx_serial_refclk is indirectly based on the rx_clk of RX SDI MegaCore.
As the FIFO starts to fill up (indicating that the transmitter is running slower than the receiver), the VXCO will be adjusted to increase frequency input to tx_serial_refclk. As the FIFO starts to empty, (indicating that the transmitter is running faster than the receiver) the VXCO will be adjusted to decrease frequency input to tx_serial_refclk. Hence, it prevents FIFO from overflowing or underflowing.
Figure 1. SDI
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