Solution ID: rd05212009_467
Last Modified: Nov 21, 2010
Product Category: Intellectual Property
Product Area: Other (Intellectual Property)
Product Sub-area: Other (IP)
Software: N/A
Device Family: N/A
IP Product: SDI Video Interface
Title
Can I use rx_clk output from RX SDI MegaCore as input to tx_serial_refclk of TX SDI MegaCore during parallel video signal loopback?
Description
The rx_clk output signal for SDI RX in SD/ HD / 3G video mode has a high amount of jitter. Therefore, rx_clk cannot be used to directly transmit data.
The general recommended approach to system clocking with the Altera® SDI Megacore function is to use an external chip such as a VCXO or a clock cleaner. The VCXO or clock cleaner should lock to the rx_clk or rx_data_valid_out signals of the RX SDI Megacore. The clean VCXO or clock cleaner output would then be used as the transmit clock (tx_serial_refclk)
Figure 1. SDI
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