Solution ID: rd06182009_437
Last Modified: Jun 25, 2010
Product Category: Intellectual Property
Product Area: Other (Intellectual Property)
Product Sub-area: Other (IP)
IP Product: Triple Speed Ethernet MAC
Title
How are the TSE register addresses in SOPC Builder calculated for the Altera Triple Speed Ethernet (TSE) MegaCore function?
Description
When using the Altera® Triple Speed Ethernet MegaCore® function and accessing TSE registers in an SOPC system, bits 0 and 1 of the address are omitted.
For example:
To access the MAC scratch register (offset of 0x04), the address is 0x01.
Calculation: 0x04 / 4
To access PCS if_mode register (offset 0x28), the address is 0x94.
Calculation : (0x200 + 0x28 * 2) / 4
(0x200 is the PCS register base address)
To access the MAC register, the address is:
address = MAC Register Address Offset / 4;
To access the PCS register, the address is:
address = (PCS Base Address Offset + PCS Register Address Offset * 2) / 4
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