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Solution ID: rd06252007_878
Last Modified: Aug 28, 2007
Product Category: Design Software
Product Area: Design Entry/Planning
Product Sub-area: VHDL
Problem
How do I implement open drain outputs in the Quartus II software?
Solution
You can implement an open drain output signal using standard VHDL or Verilog HDL statements, or by instantiating an Altera® open drain (OPNDRN) primitive.
Method 1. Use one of the following HDL statements to create an open drain output for a signal called top_out:
VHDL: top_out <= 'Z';
Verilog HDL: assign top_out = 1'bZ;
Method 2. Use the Altera OPNDRN primitive to create an open drain output. This primitive is defined in Quartus® II Help as described below.
VHDL:
<instance_name>: opndrn PORT MAP (
a_in => <input_wire>,
a_out => <output_pin>
);
The VHDL component is declared in an Altera primitives library. Use the following commands to include the library:
LIBRARY altera;
USE altera.altera_primitives_components.all;
Verilog HDL:
OPNDRN <instance_name> (.in(<input_wire>), .out(<output_pin>));
You can use the Quartus II language templates to help you instantiate the primitive. Right-click in the Quartus II text editor and choose Insert Template. In the Language templates list, expand the list for VHDL or Verilog HDL, then expand Altera Primitives, and then Buffers. Choose the OPNDRN primitive and click Insert. You can then customize the instantiation and continue design entry.
To confirm that the open drain output pin was implemented, check the Compilation Report. In the Fitter section of the report, expand the Resource Section and click Output Pins. The Open Drain column indicates yes for any open drain output pins.
Feedback
Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
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