Solution ID: rd09082009_706
Last Modified: Nov 10, 2010
Product Category: Devices
Product Area: PLL/Clock Management
Product Sub-area: PLL Reconfiguration
Device Family: CYCLONE III
Title
Why do I see glitches on the output port of a clock control block in Cyclone III devices when I have ensure glitch free switchover enabled?
Description
There is a bug in Quartus® II software version 9.0 SP2 and previous versions which affects the "ensure glitch-free switchover implementation" in the Cyclone® III device altclkcntrl megafunction. If you select this option, close the megawizard, then later open the altclkcntrl instantiation, you will see the "ensure glitch-free switchover implementation" is not selected. Due to this bug, the altclkcntrl design files created by the MegaWizard™ Plug In Manger will not enable the glitch-free implementation feature.
This problem can be fixed by installing the following patch for Quartus II software version 9.0 SP2. You will need to open your altclkcntrl megafunction instantiation and enable the "ensure glitch-free switchover implementation" option and recompile your project after you have installed the patch.
- Quartus II software version 9.0 SP2 Windows Patch 2.54
- Quartus II software version 9.0 SP2 Linux Patch 2.54
This issue is fixed in Quartus II software version 9.1.
Feedback
Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
