Solution ID: rd11292007_918
Last Modified: Mar 19, 2009
Product Category: Devices
Product Area: External Memory Interface
Product Sub-area: DLL/DQS Circuitry
Device Family: ARRIA GX,HARDCOPY,HARDCOPY II,STRATIX,STRATIX GX,STRATIX II,STRATIX II GX

Title

What is the minimum number of DLL clock cycles required during an SDRAM refresh cycle for Stratix, Stratix GX, Stratix II, Stratix II GX, HardCopy, HardCopy II and Arria GX devices?

Description

If the DLL reference clock is stopped and restarted thereafter, such as during an SDRAM refresh cycle, a minimum of 16 clock cycles is needed before data can be captured properly in Stratix®, Stratix GX, Stratix II, Stratix II GX, HardCopy®, HardCopy II and Arria GX® devices.

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