Solution ID: rd12022005_271
Last Modified: Dec 13, 2005
Product Category: Embedded
Product Area: Hardware Development
Product Sub-area: Simulation

Problem

Why do I not see any activity on the processor bus when simulating a VHDL Nios^® II processor design in the ModelSim^® tool?

Solution

When simulating the VHDL reference designs that ship with the Nios II development kit the input clock to the system will drive an 'X' instead of logical values. This causes simulations to fail as the processor remains in a reset state. Verilog designs are not affected by this problem.

The processor clock is driven via a phased locked loop (PLL). The corresponding <PLL module name>.vhd file instantiates a lower level module called altpll<PLL module name>. The setup_sim.do script generated by the SOPC Builder tool incorrectly compiles the <PLL module name>.vhd file before altpll<PLL module name>.vhd. To correct this problem modify the setup_sim.do script to compile altpll<PLL module name>.vhd before the <PLL module name>.vhd file.

The PLL also requires a simulator resolution of picoseconds whereas the setup_sim.do script uses a resolution of nanoseconds. Modify the setup_sim.do script to use a resolution of picoseconds by changing the following lines:

if { [ vsimAuth ] == "ALTERA" } {
alias _vsim {vsim +nowarnTFMPC -L lpm -L altera_mf -L sgate test_bench } } else {
alias _vsim {vsim +nowarnTFMPC test_bench } }

to read:

if { [ vsimAuth ] == "ALTERA" } {
alias _vsim {vsim -t ps +nowarnTFMPC -L lpm -L altera_mf -L sgate test_bench } } else {
alias _vsim {vsim -t ps +nowarnTFMPC test_bench } }

After saving the setup_sim.do script rerun the script in ModelSim by typing:

do setup_sim.do

You can then rerun the simulation and the pll will correctly drive the input clock port.

Note that SOPC Builder generation overwrites the setup_sim.do file. Therefore, you should make a backup copy of the modified setup_sim.do file.

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Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.