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FPGA Configuration Troubleshooter

Home > Support > Knowledge Database > FPGA Configuration

You can use this troubleshooter to help you identify possible causes to a failed FPGA configuration attempt. While this troubleshooter does not cover every possible case, it does identify a majority of problems encountered during configuration. This troubleshooter can be supplemented with Altera's Knowledge Database to help you identify and fix your configuration problem.

What is your configuration issue?

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  • Quartus II programmer
    • The Quartus II programmer fails to recognize the device ID
    • The Quartus II programmer reports successful configuration but the device/devices are not configured
    • Fail to initiate the EPCS or flash programming in Quartus II software
    • Fail to program the EPCS device through Serial Flash Loader (SFL)
    • Fail to program the parallel flash through Parallel Flash Loader (PFL)
  • Configuration Cycle
    • The device does not enter user mode although the CONF_DONE pin is released high at the end of the configuration cycle
    • The nSTATUS pin is pulled low or is toggling at the beginning of the configuration cycle
    • The nSTATUS pin is pulled low or is toggling at the end or at different point of the configuration cycle
    • The nCONFIG and nSTATUS pins are released high, but the CONF_DONE pin does not go high at the end
      of the configuration cycle
    • The nCONFIG and/or nSTATUS pins do not release high after the device is powered up
  • Decompression
    • Uncompressed file works but compressed file doesn't work or vice versa
  • Design Security
    • Unencrypted file works but encrypted file doesn't work or vice versa
    • Volatile key programming failure
    • Non-volatile key programming failure
    • The nSTATUS pin is pulled low or is toggling at the beginning of the configuration cycle
  • Remote System Upgrade
    • When using Remote System Upgrade feature, the FPGA is not able to switch from factory page to
      application page
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  • Altera Troubleshooters
    • Overview
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    • Simulating with ModelSim
    • Timing Analysis
    • PLL Loss of Lock
    • FPGA Configuration
    • JTAG Config & ISP
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