FPGA, CPLD, and ASIC solutions from Altera
  • Download Center
  • Literature
Sign in/register
myAltera Account
Welcome
  •   myAltera
  •   Logout
  • Products
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design & Support Services
    • Literature
  • End Markets
    • Automotive
    • Broadcast
    • Computer & Storage
    • Consumer
    • Industrial
    • Medical
    • Military
    • Test & Measurement
    • Wireless
    • Wireline
  • Technology
    • DSP
    • External Memory
    • Embedded Processing
    • Transceivers
    • Parallel I/O
    • Signal Integrity
    • System Integration
  • Training
    • Training Courses
    • University Program
    • Webcasts & Videos
    • Demonstrations
    • Events Calendar
  • Support
    • Design & Support Resources
    • Knowledge Database
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design Examples
    • Downloads
    • User Communities/Forums
    • mySupport
  • About Altera
    • About Us
    • Environmental
    • Customer Successes
    • Partners
    • Newsroom
    • Investor Relations
    • Jobs
    • Contact Us
  • Buy Online
    • Devices
    • Design Software
    • Development & Education Kits
    • Cables & Programming Hardware
    • Intellectual Property
  • Entire Site
  • Part Number
  • Knowledge Database
  • Support & Technical Docs
  • Forums & Wiki
Username:  
Password:  
 
Forgot my username or password
Don't have myAltera account? Register Now.
Enter your email address:

DMB-TH Reference Design

Home > Support > Reference Designs > Broadcast > DMB-TH Reference Design

from Tsinghua University

Request Reference Design
OpenCore Support

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

Overview

DMB-TH is a Chinese digital terrestrial television standard, GB20600-2006, for transmitting SD and HD television. The platform is based on an Altera® Stratix® II FPGA. The Stratix II FPGA provides the heart of the baseband digital signal processing (DSP) for channel coding, modulation and filtering that are required to meet the GB20600-2006 standard.

Features

  • Framing structure
  • Channel coding
  • Digital QAM modulation
  • PN sequence frame header for fast synchronization and highly efficient channel
    estimation / equalization
  • LDPC FEC coding
  • Supports payload data rates of 4.813 Mbps to 32.486 Mbps
  • SDTV and HDTV
  • Mobile and stationary transmission
  • MFN and SFN

Figure 1 DMB-TH Schematic Diagram

Figure 1 DMB-TH Schematic Diagram

Devices Targeted

Stratix II and Stratix III FPGAs

Demonstrated Altera Technology

  • Stratix II FPGAs

Deliverables

  • Source code
  • Reference design for DSP Development Kit, Stratix II Edition (DK-DSP-2S60N)
  • Pre-compiled library test bench for ModelSim®-Altera
  • Full documentation
    • User Guide
    • Programmer Guide Simulation tutorial
    • DMB-TH specification
    • Application Note
    • IP performance report

Contact Information

Dr. Pan Changhong
Tsinghua University
DTV  R&D Center
Room 1-408 FIT Building No. 1
Qinghuayuan, Haidian District, Beijing China
Email: pcy@tsinghua.edu.cn
Website: www.tsinghua.edu.cn

Reference Designs Disclaimer

These reference design illustrations remain the copyrighted property of Altera or its licensors and may be used within Altera Corporation devices only. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.

Rate This Page


  • IP & Reference Designs
    • All Intellectual Property
    • All Reference Designs
    • Bridges & Adapters
      • Memory Mapped
      • Streaming
    • DSP
      • Filters & Transforms
      • Error Detection/Correction
      • Modulation & Demodulation
      • Video & Image Processing
    • Embedded Processors
      • Nios II
        • Processor Cores
          • Fast CPU
          • Economy CPU
          • Standard CPU
        • Benefits
          • Low Cost
          • High Performance
          • Long Life Cycle
          • Flexibility
        • Software Tools
          • Nios II IDE
          • Nios II C2H Compiler
          • Software
        • Development Kits
        • End Markets
        • Customer Successes
        • Literature
      • 32/16-Bit Microprocessors
      • 8/4-Bit Microprocessors
    • Interface Protocols
      • Communications
      • Ethernet
      • High Speed
      • PCI
      • Serial
      • Video
    • Memory Controllers
      • DMA
      • Flash
      • On-Chip
      • SDRAM
      • SRAM
    • Peripherals
      • Debug & Performance
      • Display
      • Microcontroller Peripherals
      • Multiprocessor Coord.
  • About IP
    • Designing with IP
      • IP Base Suite
    • Evaluate and Download IP
    • IP Certifications
    • System Design
    • Request IP
  • IP Partners
    • About AMPP Program
    • List of IP Partners
    Please give us feedback
    Products | End Markets | Technology | Training | Support | About Altera | Buy Online
    Jobs | Investor Relations | Contact Us | Site Map | Privacy | Legal Notice
    Copyright © 1995-2010 Altera Corporation. All Rights Reserved.
    Altera Forum
    Altera
    Forum
    Twitter
    Twitter
    RSS
    RSS
    Facebook
    Facebook
    Flickr
    Flickr
    YouTube
    YouTube
    Email Updates
    Email
    Updates