This reference design demonstrates how to interface a Nios® II embedded processor to a VGA display using a DMA-enabled VGA controller. The design contains a complete SOPC Builder-based hardware system and software that exercises the VGA controller and displays images to a VGA monitor.
Demonstrated Altera Technology
The reference design demonstrates the following Altera® technology:
- Nios II embedded processors
- SOPC Builder
- Cyclone® II FPGAs
- Stratix® II FPGAs
The reference design supports two Nios II development boards:
- Nios II Development Board, Cyclone II Edition
- Nios II Development Board, Stratix II RoHS Edition
This design also requires the use of the Lancelot daughtercard if you wish to display to a VGA monitor. The Lancelot card features a Texas Instruments THS8134 video digital-to-analog converter (DAC) with a VGA output connector, allowing you to display directly to a monitor. The Lancelot card from Microtronix attaches to the prototype headers of Nios II development boards.
The hardware portion of the reference design is created in SOPC Builder. The design contains a Nios II CPU, a VGA controller peripheral, and a minimal set of components required for simple VGA display. The VGA controller peripheral is capable of displaying the following resolutions:
- 640 x 480
- 800 x 600
- 1024 x 768
All resolutions can be displayed in either 16-bit or 24-bit color. Resolution and color depth settings are configurable in the VGA Controller configuration wizard in SOPC Builder.
The software portion of the design is a simple application that demonstrates how to initialize the VGA controller, and then begins writing graphics data to the VGA display. The software source includes a small graphics library capable of displaying text, lines, and simple shapes. The graphics library is demonstrated by rotating a multi-colored cube on the VGA display.
Hardware Design Specifications
- Board support
- Nios Development Board, Cyclone II edition
- Nios Development Board, Stratix II RoHS edition
- Nios II/f CPU core, 4 Kbytes I-cache, 4 Kbytes D-cache—1
- System timer—1
- On-chip RAM—1 Kbyte
- Off-chip synchronous SRAM—1 Mbyte
- Common flash interface (CFI) flash memory interface—8 Mbytes
- SDRAM controller—32 Mbytes
- JTAG UART—1
- System ID peripheral—1
- Phase-locked loops (PLLs)—2
Figure 1. Nios II VGA System Block Diagram
Reference Design Files
The reference design is downloadable as a .zip file. The .zip file contains all the necessary hardware and software files to reproduce the example, as well as a readme.txt file. The readme.txt file contains instructions for re-building and running the design.
The VGA controller SOPC Builder component is included in the VGA_Controller directory of the extracted project. Inside the VGA_Controller directory, there is a sub-directory named .doc, which contains a block diagram and documentation for the VGA Controller component.
Reference Designs Disclaimer
These reference design illustrations may be used within Altera Corporation devices only and remain the copyrighted property of Altera. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.