FPGA, CPLD, and ASIC solutions from Altera
  • Download Center
  • Literature
Sign in/register
myAltera Account
Welcome
  •   myAltera
  •   Logout
  • Products
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design & Support Services
    • Literature
  • End Markets
    • Automotive
    • Broadcast
    • Computer & Storage
    • Consumer
    • Industrial
    • Medical
    • Military
    • Test & Measurement
    • Wireless
    • Wireline
  • Technology
    • DSP
    • External Memory
    • Embedded Processing
    • Transceivers
    • Parallel I/O
    • Signal Integrity
    • System Integration
  • Training
    • Training Courses
    • University Program
    • Webcasts & Videos
    • Demonstrations
    • Events Calendar
  • Support
    • Design & Support Resources
    • Knowledge Database
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design Examples
    • Downloads
    • User Communities/Forums
    • mySupport
  • About Altera
    • About Us
    • Environmental
    • Customer Successes
    • Partners
    • Newsroom
    • Investor Relations
    • Jobs
    • Contact Us
  • Buy Online
    • Devices
    • Design Software
    • Development & Education Kits
    • Cables & Programming Hardware
    • Intellectual Property
  • Entire Site
  • Part Number
  • Knowledge Database
  • Support & Technical Docs
  • Forums & Wiki
Username:  
Password:  
 
Forgot my username or password
Don't have myAltera account? Register Now.
Enter your email address:

Cyclone III Active Parallel Remote System Upgrade Reference Design

Home > Support > Reference Designs > Industrial & Military > Cyclone III Active Parallel Remote System Upgrade Reference Design

from Altera Corporation

View Literature
Download Reference Design



The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

Overview

System designers face difficult challenges today such as shortened design cycles, evolving standards and system deployments in remote locations. Cyclone® III FPGAs help overcome these challenges with its inherent re-programmability and dedicated circuitry to perform remote system upgrades (RSUs). Cyclone III FPGAs support the RSU feature in active parallel (AP) and active serial (AS) mode.

This reference design shows you how to use the Cyclone III RSU feature in AP mode. Cyclone III FPGAs are able to receive new configuration data from a remote source, update the flash memory content, and reconfigure itself with the new configuration data. In this reference design example, user logic is instantiated in the design to interface with the altremote_update megafunction, directing the RSU circuitry to initiate the reconfiguration cycle. The user logic is written specifically to complement the altremote_update megafunction and educates you on altremote_update megafunction usage. This document is targeted for the Cyclone III Starter Kit Board and is useful to get started with the RSU feature using the Cyclone III FPGAs.

Demonstrated Altera Technology

  • Cyclone III FPGA Family

Related Links

  • AN 521: Cyclone III Active Parallel Remote System Upgrade Reference Design (PDF)
  • Cyclone III FPGA Starter Kit
  • Cyclone III FPGA Development Kit

Reference Designs Disclaimer

These reference design illustrations may be used within Altera Corporation devices only and remain the copyrighted property of Altera. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.

Rate This Page


  • IP & Reference Designs
    • All Intellectual Property
    • All Reference Designs
    • Bridges & Adapters
      • Memory Mapped
      • Streaming
    • DSP
      • Filters & Transforms
      • Error Detection/Correction
      • Modulation & Demodulation
      • Video & Image Processing
    • Embedded Processors
      • Nios II
        • Processor Cores
          • Fast CPU
          • Economy CPU
          • Standard CPU
        • Benefits
          • Low Cost
          • High Performance
          • Long Life Cycle
          • Flexibility
        • Software Tools
          • Nios II IDE
          • Nios II C2H Compiler
          • Software
        • Development Kits
        • End Markets
        • Customer Successes
        • Literature
      • 32/16-Bit Microprocessors
      • 8/4-Bit Microprocessors
    • Interface Protocols
      • Communications
      • Ethernet
      • High Speed
      • PCI
      • Serial
      • Video
    • Memory Controllers
      • DMA
      • Flash
      • On-Chip
      • SDRAM
      • SRAM
    • Peripherals
      • Debug & Performance
      • Display
      • Microcontroller Peripherals
      • Multiprocessor Coord.
  • About IP
    • Designing with IP
      • IP Base Suite
    • Evaluate and Download IP
    • IP Certifications
    • System Design
    • Request IP
  • IP Partners
    • About AMPP Program
    • List of IP Partners
    Please give us feedback
    Products | End Markets | Technology | Training | Support | About Altera | Buy Online
    Jobs | Investor Relations | Contact Us | Site Map | Privacy | Legal Notice
    Copyright © 1995-2010 Altera Corporation. All Rights Reserved.
    Altera Forum
    Altera
    Forum
    Twitter
    Twitter
    RSS
    RSS
    Facebook
    Facebook
    Flickr
    Flickr
    YouTube
    YouTube
    Email Updates
    Email
    Updates