Edge Detection Reference Design
from Altera Corporation
OverviewVideo and image processing applications are typically very computationally intensive. Given the increasing processing demands, the parallel processing capabilities of Altera® programmable logic devices (PLDs) make them an attractive implementation option for highly repetitive tasks found in video and imaging functions. Instead of using multiple programmable digital signal processors, a single FPGA with an embedded Nios® II processor can deliver the requisite level of computing performance more cost-effectively, while simplifying board complexity. The Altera Stratix®II device family—with its dedicated digital signal processing (DSP) blocks, TriMatrix memory, and on-chip phase-locked loops (PLLs)—is particularly well-suited for the demands of video and image processing functions. In addition, by combining the use of Altera system development tools, parameterizable DSP cores, and Stratix II devices, complex, high-performance DSP designs can be implemented in a relatively short period of time. Altera provides an edge detection reference design to illustrate the benefits of using Altera FPGAs for video and imaging applications. The reference design demonstrates key features of the DSP Development Kit, Stratix II Edition and shows how to use Altera’s DSP Builder tool for modeling and simulating an imaging design. The combined MATLAB and Simulink environment provides an easy interface to import and export data to and from the DSP Builder design in order to read and display images, while verifying the functionality of the Stratix II design. The edge detection reference design is implemented using a combination of hardware and software components. The edge detection module built in DSP Builder is seamlessly integrated into the overall system using the built-in SOPC Builder interface (see Figure 1). In addition to the Nios II processor, the edge detection design uses both custom and standard peripherals found in the SOPC Builder library, the Altera library of parameterizable modules (LPM), and additional custom logic. The targeted device on the Stratix II EP2S60 DSP development board is the Altera EP2S60F1020C4. Demonstrated Altera TechnologyThe edge detection reference design demonstrates the following Altera technology: Block DiagramFigure 1 shows a block diagram of SOPC Builder. Figure 1. SOPC Block Diagram 
Related LinksReference Designs DisclaimerThese reference design illustrations may be used within Altera Corporation devices only and remain the copyrighted property of Altera. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
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