from Altera Corporation
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Overview
Altera offers a PCI Express to DDR2 SDRAM reference design that demonstrates the operation of Altera's PCI Express (PCIe) MegaCore® product. This reference design provides an interface between the Altera® PCIe MegaCore function and the Altera DDR2 SDRAM High-Performance Controller MegaCore function that enables access to external DDR2 SDRAM memory through the PCIe bus. It also represents an example of a typical user application that interfaces to the system side of the Altera PCIe MegaCore function.
Features
- Supports PCIe root complex to PCIe end point memory read and write transactions
- Supports PCIe end point to PCIe root complex direct memory access (DMA) read and write transactions
- Uses the PCIe hard IP MegaCore function
- Demonstrates how to use the DDR2 SDRAM High-Performance Controller MegaCore function
- Supports Arria® II GX FPGAs with internal transceivers
Demonstrated Altera Technology
- Arria II GX FPGAs with transceiver technology
- Altera PCIe MegaCore function
- Altera DDR2 SDRAM High-Performance Controller MegaCore function
Block Diagram
Related Links
- Arria II GX FPGAs
- Altera PCI Express MegaCore Function
- Altera DDR2 SDRAM High-Performance Controller MegaCore Function
- AN 575: PCI Express to DDR2 SDRAM Reference Design (PDF)
Reference Designs Disclaimer
These reference design illustrations may be used within Altera Corporation devices only and remain the copyrighted property of Altera. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
