Altera Home Page
Literature Licensing
Buy On-Line Download

  Home   |   Products   |   Support   |   End Markets   |   Technology Center   |   Education & Events   |   Corporate   |   Buy On-Line  
  Knowledge Database   |   Devices   |   Design Software   |   Intellectual Property   |   Design Examples   |   mySupport   |   Reference Designs  

 By End Market
      Automotive
      Broadcast
      Computing
      Consumer
      Industrial & Military
      Wireless
      Wireline
  
 By Device
      Stratix IV
      Stratix III
      Stratix II
      Stratix II GX
      Stratix
      Stratix GX
      Arria GX
      Cyclone III
      Cyclone II
      Cyclone
      MAX II
  
 By Intellectual Property
      Embedded Processors
      Interfaces & Peripherals
      DSP
      Communications
  

DFT/IDFT Reference Design for 3GPP LTE

from Altera Corporation

View Literature



Please contact your local Altera sales representative for a copy of this reference design. The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

Overview

You can use the Altera® discrete Fourier transform (DFT)/inverse DFT (IDFT) reference design to accelerate the implementation 3rd Generation Partnership Project (3GPP) long term evolution (LTE)-based wireless networks. DFT/IDFT is a key component of the LTE PHY layer, with the DFT functionality being required on the terminal side and IDFT on the basestation side. This reference design demonstrates the suitability of Stratix® and Arria® series FPGAs  for implementing high-performance, low-latency DFT/IDFT functionality.

Altera supplies the reference design as clear-text VHDL, including a fixed-point MATLAB simulation model.

Features

  • Supports all of the 34 transform sizes specified in the 3GPP LTE standard
  • Supports run-time configuration on a block-by-block basis between the transform sizes
  • User-defined inputs for specifying transform mode (DFT or IDFT) and internal bit widths
  • Supports complex input and output sequences
  • Highly optimized design targeting efficient use of Stratix II and Stratix III FPGA resources

Demonstrated Altera Technology

Block Diagram

Figure 1 shows the DFT/IDFT reference design blocks.

Figure 1. DFT/IDFT Reference Design Blocks

Figure 1. DFT/IDFT Reference Design Blocks

Related Links

Reference Designs Disclaimer

These reference design illustrations may be used within Altera Corporation devices only and remain the copyrighted property of Altera. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.

  Please Give Us Feedback