EMIF Co-Processor Reference Design

from Altera Corporation

The EMIF co-processor reference design demonstrates the use of an Altera^® FPGA as a high-performance digital signal processing (DSP) co-processor to the Texas Instruments TMS320C6000 family of programmable digital signal processors. The hardware interface is a connection between the TI digital signal processor’s external memory interface (EMIF) and the first-in first-out (FIFO) buffers on the FPGA. The reference design utilizes TI’s TMS320C6416 DSP Starter Kit (DSK), which features a TI TMS320C6416 device and the Altera Stratix^® II DSP development board, which features an EP2S60F1020C4 FPGA. The reference design is supplied with Verilog HDL and TI DSP source code. Altera also supplies example software to demonstrate the use of the reference design.

Demonstrated Altera Technology

The EMIF co-processor reference design demonstrates the following Altera technology:

• Stratix II Devices
• Fast Fourier Transform (FFT) MegaCore^® Function

Block Diagram

A block diagram of the Stratix II DSP development board is shown in Figure 1.

Figure 1. Stratix II DSP Development BoardBlock Diagram

Related Links

• DSP Development Kit, Stratix II Edition
• AN 363: FFT Co-Processor Reference Design
• Request a CD-ROM of This Reference Design

Reference Designs Disclaimer

These reference design illustrations may be used within Altera Corporation devices only and remain the copyrighted property of Altera. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.