High-Speed Interface for Fujitsu MB86064 DACs Reference Design
from Altera Corporation
OverviewImplementing the digital interface to drive a high-speed digital-to-analogue converter (DAC) is challenging. The conversion rates of high-speed DACs have increased significantly in recent years, so special design techniques are required to ensure data integrity. This Altera®reference design, which implements a high-speed data interface between a Stratix®device and aFujitsu MB86064 DAC, comprises two 14-bit parallel buses, each running at up to 800 million samples per second (MSPS). A key feature of the reference design combines the Stratix enhanced phase-locked loop (PLL) with the MB86064 loop-clock facility to maintain optimum clock-to-data timing. Demonstrated Altera TechnologyBlock DiagramFigure 1. Block Diagram 
Click image for a larger view.
Notes: PLD = programmable logic device SERDES = serializer/deserializer LVDS = low-voltage differential signaling DDR = double data rate SDR = single data rate
Related LinksReference Designs DisclaimerThese reference design illustrations may be used within Altera Corporation devices only and remain the copyrighted property of Altera. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
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