Link-Port Reference Design
from Altera Corporation
Overview
The link-port reference design implements link-port transmitters and receivers in Altera® FPGAs. The link-port interface is a high-speed communications interface available on Analog Devices TigerSharc TS20x digital signal processors with a LVDS electrical interface using double data rate (DDR) data. Each link-port interface is either a transmitter or a receiver with one or four data pins, an LVDS clock, and a number of single-ended status signals. The link-port interface has the following features:
- Discontinuous clock that runs only when data is being transmitted
- Quad word (128-bit) minimum data size
- Optional checksum byte
Altera supplies the reference design as Verilog hardware description language (HDL) source code. The reference design includes a testbench that allows you to test this source code.
The purpose of this reference design is to demonstrate that Stratix®, Arria®, and Cyclone® series FPGAs performance is suitable to implement link-port interfaces to Analog Devices TigerSharc TS20x digital signal processors.
Demonstrated Altera Technology
Block Diagram
Figure 1. Transmitter Block Diagram
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Reference Designs Disclaimer
These reference design illustrations remain the copyrighted property of Altera and may only be used within Altera Corporation devices. They are provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
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