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Home > Support > Reference Designs > Wireline > PCI to Local Bridge Reference Design Print This Page Subscribe to Email PCI to Local Bridge Reference Design from Dexcel Electronics Designs   Overview Most PCI chips and cores only implement the minimum PCI bus interface signaling. This leaves the burden of connectivity, performance, and system compatibility on the designer. This reference design  illustrates how you can enhance the Altera® pci_t32 MegaCore® function to provide a set of advanced features to provide the best possible performance and flexibility to simplify the design. The design implements a 32-bit 66-MHz local bus. Features PCI local bus specification r2.2 vital product data configuration support Flexible local bus provides 32-bit multiplexed or non-multiplexed protocol for 8-, 16-, or 32-bit peripheral and memory devices Nine programmable general-purpose I/O pins Five programmable local address spaces Four programmable chip selects Programmable local bus wait states Two programmable local-to-PCI interrupts Endian byte swapping Local address remap Demonstrated Altera Technology MAX® II CPLDs Block Diagram Figure 1. PCI to Local Bridge Reference Design Block Diagram View full detail (108 KB) Related Links MAX II devices Altera PCI MegaCore functions Reduce System Costs by Integrating PCI Interface Functions Into CPLDs White Paper (PDF) Contact Information Dexcel Electronics Designs (P) Ltd, Unit 505, Carlton Towers, #1, Airport Road Bangalore 560008, India. Tel: +91 80 25216221, 25216222 Fax: +91-80-2521 6791 info@dexceldesigns.com www.dexceldesigns.com Rate This Page

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