Single event upsets (SEUs) are caused by ionizing radiation strikes that discharge the charge in storage elements, such as configuration memory cells, user memory, and registers. In terrestrial applications, the two ionizing radiation sources of concern are alpha particles emitted from package impurities and high-energy neutrons caused by the interaction of cosmic rays with the earth's atmosphere. Studies conducted over the last 20 years have led to high purity package materials minimizing SEU effects caused by alpha particle radiation. Unavoidable atmospheric neutrons remain the primary cause for SEU effects today. Soft errors are random and happen according to a probability related to energy levels, flux, and cell susceptibility.
Altera has been studying the effects of SEUs on its devices for many process generations and has built up extensive experience in both the reduction of soft-error rates through SEU-optimized physical layout and process technology, and in soft-error mitigation techniques. Altera introduced the industry's first automatic cyclical redundancy check (CRC) and removed the extra logic and complexity requirements common to other error checking solutions. Altera's device families are all tested for SEU behavior and performance using facilities such as Los Alamos Weapons Neutron Research (WNR) using standard test procedures defined by JEDEC's JESD-89 spec.
SEU testing of Altera® FPGAs at Los Alamos Neutron Science Center (LANSCE) has revealed the following results:
- SEUs do not induce latch-up in Altera FPGAs
- No SEU errors have been observed in hard CRC circuit and I/O registers
- An SEU causes only single-bit errors within the configuration memory for products up to 65 nm and possibly multibit errors for 40 nm and beyond
- The CRC circuit can detect all single-bit and multi-bit errors within the configuration memory
- There's a Mean Time Between Functional Interrupt (MTBFI) of hundreds of years, even for very large, high-density FPGAs
Altera's Stratix® series, Arria® GX series, and Cyclone® series of FPGA families feature built-in dedicated hard circuitry to continually and automatically check CRC at no extra cost. For products manufactured on 28 nm process technology and subsequent process nodes, Altera has implemented CRAM upset bit correction (scrubbing) in addition to enhanced EDCRC detection.You can easily set up the CRC checker through Quartus® II software. Our HardCopy® ASIC family offers reliability that exceeds that of standard-cell ASICs through seamless prototyping using Stratix series FPGAs to a pin-compatible ASIC without heavy investment in design tools, chip design, or board redesign.
For more information regarding other mitigation techniques and for further details about SEU testing of Altera devices, please contact your local Altera sales representative or distributor.
- Automatic CRC Checking in Stratix Series FPGAs
- SEU Mitigation in Stratix V Devices (PDF)
- SEU Mitigation in Stratix IV Devices (PDF)
- SEU Mitigation in Arria V Devices (PDF)
- SEU Mitigation in Arria II Devices (PDF)
- SEU Mitigation in Cyclone V Devices (PDF)
- SEU Mitigation in Cyclone IV Devices (PDF)
- AN357: Error Detection and Recovery (PDF)
- AN539: Test Methodology of Error Detection and Recovery Using CRC in Altera FPGA Devices (PDF)