As FPGAs increase in performance, size, and complexity, the verification process can become a critical part of the FPGA design cycle. To alleviate the complexity of the verification process, Altera provides a portfolio of on-chip debugging tools. The on-chip debugging tools allow real-time capture of internal nodes in your design to help you verify your design quickly without the use of external equipment.
For resources on on-chip debugging, see the following:
For a brief overview of the on-chip debugging portfolio of tools and the chip planner, refer to the SignalTapTM II Embedded Logic Analyzer section on the Verification and Board Level product pages.
To search for known on-chip debugging issues and technical support solutions, use Altera's Knowledge Database. You can also visit the Altera® Forum to connect and discuss technical issues with other Altera users.
For further technical support, use mySupport to create, view, and update service requests.
On-chip Debugging Resources
Table 1 provides links to available documentation about on-chip debugging tools.
|Table 1. On-chip Debugging Reference Documentation|
|Quick Design Debugging Using SignalProbe (PDF)||
This chapter of the Quartus® II Development Software Handbook describes the SignalProbe feature. This feature makes design verification more efficient by quickly routing internal signals to I/O pins without affecting the design.
|Design Debugging Using the SignalTap II Embedded Logic Analyzer (PDF)||This chapter of the Quartus II Development Software Handbook provides a description of the verification flow using the SignalTap II embedded logic analyzer. The SignalTap II embedded logic analyzer debugs an FPGA design by probing internal signals in the design while the design is running at full speed.|
|In-system Debugging Using External Logic Analyzers (PDF)||This chapter of the Quartus II Development Software Handbook provides information about the logic analyzer interface feature. This feature connects a large set of internal device signals to a small number of output pins for debugging purposes and allows you to take advantage of advanced features in your external logic analyzer.|
|In-system Updating of Memory and Constants (PDF)||This chapter of the Quartus II Development Software Handbook describes the in-system memory content editor. This feature provides read and write access to in-system FPGA memories and constants through the JTAG interface.|
|Design Debugging Using In-system Sources and Probes (PDF)||This chapter of the Quartus II Development Software Handbook describes the in-system sources and probes feature. This feature sets up customized register chains to drive or sample any logic node in your design, providing an easy way to input simple virtual stimuli and capture the current value of instrumented nodes.|
|Transceiver Link Debugging Using the Quartus II Software (PDF)||This chapter in Quartus II handbook describes how to use the new transceiver toolkit introduced in the Quartus II software v10.0 to verify the high-speed links of Altera's transceiver-based devices in your system. Altera also provides design examples with this chapter to get you started with the transceiver toolkit.|
|sld_virtual_jtag Megafunction User’s Guide (PDF)||
This reference manual describes the Virtual JTAG megafunction, also known as the sld_virtual_jtag megafunction. The sld_virtual_jtag megafunction makes it easy to use the JTAG port as a simple communications interface, allowing you to develop custom debugging solutions.
|AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems (PDF)
This application note describes how to use the SignalTap II logic analyzer to monitor signals located inside a system module generated by SOPC Builder.Design files for AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems.
|AN 446: Debugging Nios II Systems with the SignalTap II Logic Analyzer (PDF)||This application note examines the use of the Nios® II plug-in within the SignalTap II logic analyzer and presents the capabilities, configuration options, and use-modes for the plug-in.|
Table 2 provides links to available training and demonstrations on on-chip debugging tools.
|Table 2. On-chip Debugging Training and Demonstrations|
|SignalTap II Embedded Logic Analyzer
Chinese Version: Design Debugging Using the SignalTap II Logic Analyzer
|This online training course provides an in-depth walkthrough on using the SignalTap II logic analyzer.
This is an hour and a half online course.
Learn how to verify high-speed transceiver links on your board using the transceiver toolkit (introduced in Quartus II v10.0) with this online training course.
This is 40-minute online course.
|Debugging & Communicating with an FPGA Using the Virtual JTAG Megafunction||This training is an introduction on how to use the Virtual JTAG megafunction.
This is a half hour online course.
|The Quartus II Software Design Series: Verification||Learn advanced features (including the use of on-chip debugging tools) of the Quartus II software that enable you to verify your design.
This is a one day instructor-led course.