FPGA, CPLD, and ASIC solutions from Altera
  • Download Center
  • Literature
Sign in/register
myAltera Account
Welcome
  •   myAltera
  •   Logout
  • Products
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design & Support Services
    • Literature
  • End Markets
    • Automotive
    • Broadcast
    • Computer & Storage
    • Consumer
    • Industrial
    • Medical
    • Military
    • Test & Measurement
    • Wireless
    • Wireline
  • Technology
    • DSP
    • External Memory
    • Embedded Processing
    • Transceivers
    • Parallel I/O
    • Signal Integrity
    • System Integration
  • Training
    • Training Courses
    • University Program
    • Webcasts & Videos
    • Demonstrations
    • Events Calendar
  • Support
    • Design & Support Resources
    • Knowledge Database
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design Examples
    • Downloads
    • User Communities/Forums
    • mySupport
  • About Altera
    • About Us
    • Environmental
    • Customer Successes
    • Partners
    • Newsroom
    • Investor Relations
    • Jobs
    • Contact Us
  • Buy Online
    • Devices
    • Design Software
    • Development & Education Kits
    • Cables & Programming Hardware
    • Intellectual Property
  • Entire Site
  • Part Number
  • Knowledge Database
  • Support & Technical Docs
  • Forums & Wiki
Username:  
Password:  
 
Forgot my username or password
Don't have myAltera account? Register Now.
Enter your email address:

IBIS Models

Home > Support > Design Software > Download > IBIS Models

The Ibis Altera® IBIS models are generated from HSPICE models and are based on either IBIS version 2.1, 3.2, or 4.1. The newer Altera device family models, such as Stratix® III and Cyclone® III IBIS models are generated with IBIS version 4.1. For models of Stratix II GX, Stratix II, Stratix GX, Stratix, Hardcopy® II, Hardcopy Stratix, Cyclone II, Cyclone, MAX® II, Mercury™, APEX™ II, APEX 20KC, and some APEX 20KE devices, IBIS models are generated with IBIS version 3.2. The rest of the device models are generated with IBIS version 2.1. 

Multi-Voltage Support

Altera devices support multiple voltages (VCCIO), and there are separate IBIS models for each of the supported voltages. To simplify the model identification and the corresponding voltage level, the following model names are used:

  • model_name_5 = 5.0-V VCCIO
  • model_name_33 = 3.3-V VCCIO
  • model_name_30= 3.0-V VCCIO
  • model_name_2 or model_name_25 = 2.5-V VCCIO
  • model_name_1 or model_name_18 = 1.8-V VCCIO
  • model_name_15  = 1.5-V VCCIO
  • model_name_12  = 1.2-V VCCIO

Slew Rate Control

Most Altera devices have the option of turning the slew rate on and off. The slew rate is turned on in files with an "s" or "slew" suffix . Likewise, the slew rate is turned off in files without an "s" or "slew" suffix in the signal/model name. For example:

  • model_name = slew rate off
  • model_name_s or model_name_slew  = slew rate on

The latest devices such as Cyclone III and Stratix III devices support programmable slew rate control. Cyclone III devices support three slew rate settings: slow (s), medium (m), and fast (f) for each supported I/O standard. Stratix III devices support four slew rate settings: slow (s0), medium (s1), medium fast (s2), and fast (s3). The suffix of an IBIS model name indicates the slew rate setting. For example:

  • model_name = without slew rate control support
  • model_name_m = with medium slew rate setting
  • model_name_s2 = with medium fast slew rate setting

PCI Clamp Diode

Most Altera devices have the option of turning the PCI clamp diode on and off. The PCI clamp-diode is enabled in files with a "p" or "pci" suffix in the signal/model name. Likewise, the PCI clamp-diode is disabled in files without a "p" or "pci" suffix in the signal/model name. For example:

  • model_name = PCI clamp diode off
  • model_name_p or model_name_pci = PCI clamp diode on

Corner Case Support

Altera IBIS models support all three corner cases: typical, minimum, and maximum. Each corner is defined by its specific voltage, process, and temperature range. The corner case information is available within the Altera IBIS model.

Supported I/O Standards

Altera IBIS models support a variety of I/O standards, including:

  • 3.3-V LVTTL/ LVCMOS
  • 3.0-V LVTTL/ LVCMOS
  • 2.5-V LVTTL/ LVCMOS
  • 1.8-V LVTTL/ LVCMOS
  • 1.5-V LVTTL/LVCMOS
  • 1.2-V LVTTL/LVCMOS
  • SSTL-3
  • SSTL-2
  • SSTL-18
  • SSTL-15
  • GTL+
  • HSTL-18
  • HSTL-15
  • HSTL-12 
  • 3.3-V PCI
  • 3.3-V PCI-X
  • 3.3-V PCML
  • 3.0-V PCI
  • 3.0-V PCI-X
  • LVDS
  • RSDS
  • PPDS
  • Mini-LVDS 
  • LVPECL
  • HyperTransport™ (HT)
  • CTT

Altera IBIS model names specify the supported I/O standard. The following examples show the I/O standard indication in the model name for several devices:

  • 2c_hstl18c2_cio_d18 represents a Cyclone II device model at column I/O bank with HSTL-18 class II standard
  • 1s_ttl33_io_d4 represents a Stratix device model with 3.3-V LVTTL standard
  • apex2_sstl2_in represents an APEX II device input model with 2.5-V SSTL-2 standard

Programmable Driver Current Strength

For newer Altera devices such as Cyclone series, Stratix series, and Hardcopy series, the drivers have different current strengths at various VCCIO levels. To distinguish between the models, each model name specifies the driver’s current strength, the VCCIO level, and the I/O standard. For example, the model name apex2_ttl_18v_4ma_s  specifies the following:

  • APEX II device model
  • LVTTL I/O driver
  • VCCIO = 1.8 V
  • Driver current strength = 4 mA
  • Slew rate control option on

On-Chip Termination

Some Altera devices support on-chip termination (OCT). The Altera device IBIS models that support OCT use the following model names:

  • model_name_r50 = 50-Ohm on-chip series termination without calibration
  • model_name_r25 = 25-Ohm on-chip series termination without calibration
  • model_name_r50c = 50-Ohm on-chip series termination with calibration
  • model_name_r25c = 25-Ohm on-chip series termination with calibration
  • model_name_g50c = 50-Ohm on-chip parallel termination with calibration
  • model_name_t100 = 100-Ohm differential on-chip termination

Programmable Pre-Emphasis

The dedicated LVDS transmitters on Cyclone III and Stratix III devices support programmable pre-emphasis. Cyclone III devices support two programmable pre-emphasis settings (on and off), while Stratix III devices support four programmable pre-emphasis settings: zero, low, medium, and high. The suffix of an IBIS model indicates the pre-emphasis setting. For example:

  • model_name_off = without pre-emphasis setting
  • model_name_on = with pre-emphasis setting
  • model_name_p1 = with low pre-emphasis setting

Programmable Differential Output Voltage (VOD)

Stratix III devices support four programmable VOD settings: low, medium low, medium high, and high. The suffix of an IBIS model indicates the pre-emphasis setting. For example:

  • model_name_v2 = medium high VOD setting

Package RLC Values

Altera provides the package RLC values for each device family on the IBIS Models home page.

IBIS Output File Generation with Quartus II Software

Quartus® II software version 2.0 and later automatically generates an IBIS output file to perform board-level signal integrity verification using EDA tools. For more information on generating IBIS output files with Quartus II software, see Generating IBIS Files With Quartus.

Related IBIS Links

  • ANSI/EIA Homepage on IBIS Specification
Rate This Page


  • Products
    • Quartus II
      • Basic Design Flow
        • Create Project
        • Make Assignments
        • Compile Designs
        • Analyze Results
        • Modify Settings
        • Assign Pins
    • SOPC Builder
    • MAX+PLUS II
    • ModelSim-Altera
  • Resource Centers
    • Overview
    • Installation & Licensing
    • Scripting
    • Board Design & I/O
    • Design Entry & Planning
    • Synthesis & Netlist Viewers
    • Incremental Compilation
    • Optimization
    • Power Management
    • TimeQuest Timing Analyzer
      • Clock Analysis
      • Exceptions
      • Collections
      • GUI Features
    • Classic Timing Analyzer
    • Simulation & Verification
    • On-Chip Debugging
    • HardCopy Design
    • EDA Tool Support
  • Software Resources
    • OS Support
    • Driver Installation
  • Download & Licensing
    • Download
    • Licensing
      • Licensing FAQ
    Please give us feedback
    Products | End Markets | Technology | Training | Support | About Altera | Buy Online
    Jobs | Investor Relations | Contact Us | Site Map | Privacy | Legal Notice
    Copyright © 1995-2010 Altera Corporation. All Rights Reserved.
    Altera Forum
    Altera
    Forum
    Twitter
    Twitter
    RSS
    RSS
    Facebook
    Facebook
    Flickr
    Flickr
    YouTube
    YouTube
    Email Updates
    Email
    Updates