Entering Resource Assignments

The MAX+PLUS^® II software allows you to enter a variety of resource and device assignments for your projects. Resource assignments are used to assign logic functions to a particular pin, logic cell, I/O cell, embedded cell, row, column, Logic Array Block (LAB), Embedded Array Block (EAB), chip, clique, local routing, logic option, timing requirement, or connected pin group. In MAX+PLUS II software, you can enter all types of resource and device assignments with Assign menu commands. You can also enter pin, logic cell, I/O cell, embedded cell, LAB, EAB, row, and column assignments in the MAX+PLUS II Floorplan Editor. The Assign menu commands and the Floorplan Editor all save assignment information in the ASCII Assignment & Configuration File (.acf) for the project. In addition, you can edit ACFs manually in any standard text editor or with the setacf utility.

Concept & Composer Schematics

In both Concept and Composer schematics, you can assign a limited subset of these resource assignments by assigning properties to symbols. These properties are incorporated into the EDIF netlist file(s). The MAX+PLUS II software automatically converts assignment information from the EDIF Input File into the ACF format. For information on making MAX+PLUS II-compatible resource assignments, go to the following topics:

• Assigning Pins, Logic Cells & Chips
• Assigning Cliques
• Assigning Logic Options
• Modifying the Assignment & Configuration File with the setacf Utility

Go to the Cadence Concept Schematic User Guide and Composer Reference User Guide for details on how to assign properties. Go to "Resource Assignments in EDIF Input Files" and "Assigning Resources in a Third-Party Design Editor" in MAX+PLUS II Help for more information on assignments or properties that can be assigned in Concept and Composer.

Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample Concept and Composer schematic files, which include resource assignments:

• /usr/maxplus2/examples/cadence/example6/fa2 (Concept)
• /usr/maxplus2/examples/cadence/example7/fa2 (Composer)

VHDL & Verilog HDL Design Files

For Verilog HDL- and VHDL-based designs, you must use the MAX+PLUS II software or the setacf utility to enter resource assignments. For information on using the setacf utility, go to Modifying the Assignment & Configuration File with the setacf Utility.

Related Topics:

• For information on entering assignments in the MAX+PLUS II software with Assign menu commands or in an ACF, go to "resource assignments" or "ACF, format" in MAX+PLUS II Help using Search for Help on (Help menu).

Feedback

Did this information help you?

If no, please log onto mySupport to file a technical request or enhancement.