Performing a Functional Simulation of a Composer Schematic with Verilog-XL Software

You can perform a functional simulation of a Cadence Composer schematic with the Verilog-XL simulator before compiling your project with the MAX+PLUS^® II software.

To functionally simulate a Composer schematic, follow these steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the
   MAX+PLUS II/Cadence Working Environment.

2. Create a Composer schematic and save it in your working directory, as described in Creating Composer Schematics for Use with MAX+PLUS II Software.

3. In Composer, select Simulation from the Tools drop-down list.

4. Select Verilog-XL to start the Verilog-XL Integration Control window.

5. When you are ready to compile the project, generate an EDIF netlist file <design name>.edf with the altout utility, as described in Converting Composer Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the altout Utility.

6. Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.

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