Performing a Functional Simulation of a Concept Schematic with VerilogLink & Verilog-XL Software
You can perform a functional simulation of a Concept schematic with VerilogLink and Verilog-XL software before compiling your project with the
MAX+PLUS® II software.
To functionally simulate a Concept schematic, follow these steps:
- Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment.
- Create a Concept schematic and save it in your working directory, as described in Creating Concept Schematics for Use with MAX+PLUS II Software.
- Generate the global.cmd, vloglink.cmd, verilog.cmd, and expansion.dat directive files.
- Type
vloglink <design name>  from the /<working directory>/source directory to create a vloglink.v file from the Concept schematic.
- Generate the stimulus file for the design and start the Verilog-XL simulator by typing the following command at the UNIX prompt from the /<working directory>/<design name>/source directory:
verilog -y /usr/maxplus2/simlib/concept/alt_max2/verilogUdps +libext+.v+.V <stimulus file name> vloglink.v
- When you are ready to compile the project, generate an EDIF netlist file <design name>.edf with the concept2alt utility, as described in Converting Concept Schematics into
MAX+PLUS II-Compatible EDIF Netlist Files with the concept2alt Utility
.
- Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.
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Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
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