You can use the vlog2alt utility to convert your Verilog HDL design into an EDIF netlist file. This file can then be imported into the
To convert a Verilog HDL design into an EDIF netlist file, follow these steps:
- Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment.
- Synthesize and optimize your Verilog HDL design with Synergy, as described in Synthesizing & Optimizing Verilog HDL Files with Synergy Software.
To convert your Verilog HDL design into an EDIF netlist file, type the following command at the UNIX prompt from your working directory:
vlog2alt <design name>-rundir max2 -vfiles<design name>.run1/syn.v
- Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.
Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample Verilog HDL files:
- /usr/maxplus2/examples/cadence/example11/count8.v
- /usr/maxplus2/examples/cadence/example13/rom_test.v
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