Synthesizing & Optimizing Verilog HDL Files with Synergy Software
You can create and process Verilog HDL files and convert them into EDIF input files that can be processed by the
MAX+PLUS® II Compiler. To process a Verilog HDL file with Synergy software for use with the MAX+PLUS II software, go through the following steps:
- Be sure to set up your working environment correctly, as described in Setting up the MAX+PLUS II/Cadence Working Environment.
- Create a Verilog HDL file <design name>.v using the MAX+PLUS II Text Editor or another standard text editor and save it in a working directory. Go to Creating Verilog HDL Designs for Use with MAX+PLUS II Software for more information on Verilog HDL design entry.
- Start Synergy by typing
synergy -lang verilog  at a UNIX prompt from your working directory.
- Choose Select Design (File menu) from the Synergy window and specify the following options:
- Select <design name>.v from the Verilog Files list.
- Choose the Verilog Option tab from the Select Design dialog box.
- Specify <design name>.run1 as the Run Directory.
- Type
/usr/maxplus2/simlib/concept/alt_max2/<design name>/verilog_lib/verilog.v <working directory>/ in the Library Files (-v) box.
- (Optional) If your design includes library of parameterized modules (LPM) functions, type
+define+SYNTH in the Other Compilations box.
- Choose Select Design.
- Choose the Design tab from the Select Design dialog box and set the target library:
- Type
alt_syn as the Target Library name.
- (Optional) To use the Synergy LPM synthesis capability, type
lpm_syn as the Library name in the Macro Cell Library box.
- Choose OK.
- (Optional) To view the synthesized schematic in Concept or Composer, go through the following steps:
- Select Schematic Generation (Utilities menu).
- Select either Concept or Composer in the Generate From box.
- Type
alt_max2 in the Symbol Libraries box.
- Choose Apply, then Close.
- Choose Select Design from the Select Design window.
- Choose Synthesize (Synthesis menu) from the Synergy window and specify the following options:
- Click on the Synthesize tab.
- Turn on the Generate Schematic option.
- Select either Composer or Concept from the Type list box.
- Choose Synthesize to start synthesizing your design.
- Generate an EDIF netlist file that can be compiled by the MAX+PLUS II Compiler, as described in Converting Verilog HDL Designs into MAX+PLUS II-Compatible EDIF Netlist Files.
- Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.
Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample Verilog HDL files:
- /usr/maxplus2/examples/cadence/example11/count8.v
- /usr/maxplus2/examples/cadence/example13/rom_test.v
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Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
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