Performing a Timing Simulation with Verilog-XL Software

Once the MAX+PLUS^® II software has compiled a project and generated a Verilog Output File (.vo), you can perform a timing simulation using Cadence Verilog-XL software.

To simulate Verilog output files with the Verilog-XL timing simulator, follow these steps:

Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment.
Generate Verilog Output Files (.vo), as described in Compiling Projects with MAX+PLUS II Software. The MAX+PLUS II Compiler generates the <design name>.vo and alt_max2.vo files for use with Verilog-XL software.
Using any standard text editor, create a stimulus file that includes test vectors for your design.
Start the Verilog-XL simulator and simulate your Verilog output files by typing the following command at the UNIX prompt:

verilog <stimulus filename(s)> <design name> alt_max2.vo

Feedback

Did this information help you?

If no, please log onto mySupport to file a technical request or enhancement.

Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.

Rate This Page

Username:
Password:
	Remember me