Click on one of the following tool names for information on using it with the
Design Entry
- Composer (Cadence)
- Concept (Cadence)
- Design Architect (Mentor Graphics)
Synthesis & Optimization
- Certify (Synplicity)
- Design Compiler (Synopsys)
- FPGA Compiler (Synopsys)
- FPGA Express (Synopsys)
- Galileo Extreme (Exemplar Logic)
- Leonardo (Exemplar Logic)
- Synergy (Cadence)
- Synplify (Synplicity)
Simulation
- Design Viewpoint Editor (see QuickSim II)
- Leapfrog (Cadence)
- QuickHDL and QuickHDL Pro (Mentor Graphics)
- QuickSim II (Mentor Graphics)
- RapidSIM (Cadence)
- Verilog-XL (Cadence)
- VHDL System Simulator [VSS] (Synopsys)
Timing Analysis/Verification
- MOTIVE and MOTIVE for Powerview (Viewlogic)
- PrimeTime (Synopsys)
- QuickPath (Mentor Graphics)
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