Instantiating the clklock Megafunction in Design Architect Schematics
You can instantiate the Altera®Âprovided clklock phase-locked loop megafunction, which is supported for some FLEX® 10K devices, in a Design Architect schematic.
To instantiate the clklock megafunction in a Design Architect schematic, follow these steps:
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Choose Altera Libraries (Library menu).
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Choose ALTERA GENLIB (Altera Libraries menu).
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Choose clklock (ALTERA GENLIB menu).
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Specify appropriate values for the CLOCKBOOST and INPUT_FREQUENCY variables. Choose Megafunctions/LPM from the MAX+PLUS® II Help menu for detailed information on the clklock megafunction.
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Choose OK.
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Continue with the steps necessary to complete your Design Architect schematic, as described in Creating Design Architect Schematics for Use with MAX+PLUSÂ II Software.
Installing the AlteraÂprovided MAX+PLUSÂ II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the sample Design Architect schematic file /usr/maxplus2/examples/mentor/example7/fifo, which includes clklock megafunction instantiation.
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Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
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