Creating Hierarchical Projects with Design Architect Software
If you wish to create a hierarchical schematic design that contains symbols representing other design files, such as AHDL Text Design Files (.tdf), VHDL Design Files (.vhd), or Verilog Design Files (.v), you can create a hollow-body symbol for the design file and then instantiate it in your top-level design file.
To create a hollow-body symbol for a lower-level design file, follow these steps:
- (Optional) If you are creating a hollow-body symbol for a VHDL or Verilog HDL design file, you can first functionally simulate the VHDL or Verilog HDL file, as described in Performing a Functional Simulation with QuickHDL Software.
- Start the Design Architect software by double-clicking Button 1 on the max2_da icon in the Design Manager tools window. You can also start Design Architect software by typing
max2_da  at the UNIX prompt.
- Choose the OPEN SYMBOL button in the Design Architect session_palette to open the Symbol Editor. Type the lower-level design file name, including the directory path, in the Component Name box. Choose OK.
- Create a symbol that represents the inputs and outputs of the lower-level file.
- Assign
PINTYPE properties of IN or OUT to the inputs and outputs of the symbol, and assign appropriate values to any other properties of the symbol so that it can be identified in the top-level schematic.
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If you are creating a hollow-body symbol for a VHDL design file, be sure to assign the value qvpro to the symbol's model property so that it can be identified as a VHDL component in the top-level schematic. |
- Check and save the symbol, then close the Symbol Editor.
- To enter the symbol, choose the CHOOSE SYMBOL button from the Design Architect session_palette.
- Select the symbol file from the Navigator menu and choose OK.
- The MAX+PLUS® II software uses the Altera®provided mnt8_bas.lmf Library Mapping File to map Design Architect symbols to equivalent MAX+PLUS II logic functions. To use custom symbols, you must create a custom LMF that maps your custom symbols to the equivalent EDIF Input File, Text Design File (TDF), or other design file. You will also need to specify this LMF in the EDIF Netlist Reader Settings dialog box before compiling the design with the MAX+PLUS II software. See Compiling Projects with MAX+PLUS II Software for more information.
- Continue with the steps necessary to complete your Design Architect schematic, as described in Creating Design Architect Schematics for Use with MAX+PLUS II Software.
Installing the Alteraprovided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the sample hierarchical Design Architect schematic file /usr/maxplus2/examples/mentor/example3/fulladd2.
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Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
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