Creating Design Architect Schematics for Use with MAX+PLUS II Software

You can create Design Architect schematics and convert them into EDIF Input Files (.edf) that can be processed with the MAX+PLUS^® II Compiler.

To create a Design Architect schematic for use with MAX+PLUS II software, go through the following steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.
2. Start the MAX+PLUS II/Mentor Graphics interface by typing max2_dmgr at a UNIX prompt.
3. Start the Design Architect software by double-clicking Button 1 on the max2_da icon in the Design Manager tools window. You can also start Design Architect software by typing max2_da  at the UNIX prompt.
4. Use the graphical user interface to structure and organize your files to create an environment that facilitates entering and processing designs. Go to the following topics for more information:
   • Local Work Area Directory Structure
   • MAX+PLUS II Project Directory Structure
   • Mentor Graphics Project Directory Structure
5. Choose the OPEN SHEET button in the Design Architect session_palette, then specify a name for your project in the Component Name box. Choose OK.
6. Enter logic functions from the following Altera^®­provided libraries:
   • ALTERA LPMLIB includes library of parameterized modules (LPM) functions
   • ALTERA GENLIB includes primitives and macrofunctions
   • LSTTL includes 74-series macrofunctions
   
   

   You can instantiate MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPPSM). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support.

   The following topics describe special steps needed to instantiate LPM and clklock functions:

   • Instantiating LPM Functions in Design Architect Schematics
   • Instantiating the clklock Megafunction in Design Architect Schematics
7. (Optional) To create a hierarchical design that contains symbols representing other design files, such as AHDL or VHDL design files, go to Creating Hierarchical Projects with Design Architect Software.
8. If you wish to make resource assignments in a Design Architect schematic, go to Entering Resource Assignments. You can also enter resource assignments from within the MAX+PLUS II software.
9. Choose Check Sheet for Altera (Check menu) to save and check your design. If your design contains LPM functions , the Design Architect software will ask whether you want to compile the LPM model. Choose YES if you want to compile the VHDL code for the LPM functions. The software will automatically select the corresponding compiler: System 1076 for B.(x) releases and QuickHDL compilers for releases C.1 and later.
10. (Optional) If your schematic design includes models for VHDL or Verilog HDL designs, perform a functional simulation with the QuickHDL Pro software, as described in Performing a Functional Simulation with QuickHDL Pro Software. If it does not, you can perform a functional simulation with the QuickSim software, as described in Performing a Functional Simulation with DVE & QuickSim II Software.
11. Once you have created a schematic, you can generate an EDIF netlist file that can be imported into the MAX+PLUS II software with either of the following methods:
    • You can create an EDIF netlist file, as described in Converting Design Architect Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the ENWrite Utility.
    • You can use the Altera Schematic Express utility, sch_exprss, to automatically create an EDIF netlist file, compile it with the MAX+PLUS II Compiler, generate an EDIF Output File (.edo), and prepare the EDIF Output File for simulation with ENRead and Design Viewpoint Editor (DVE), as described in Using the Altera Schematic Express (sch_exprss) Utility.

    Even if your design is a hierarchical design incorporating files created with multiple design entry methods, both the ENWrite and Altera Schematic Express utilities generate EDIF files for all files in the design.

Installing the Altera­provided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the following sample Design Architect schematic files:

• /usr/maxplus2/examples/mentor/example1/fulladd
• /usr/maxplus2/examples/mentor/example3/fulladd2
• /usr/maxplus2/examples/mentor/example7/fifo

Related Links:

• Go to Compiling Projects with MAX+PLUS II Software in these MAX+PLUS II ACCESS^SM Key topics for related information.

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Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.