Creating VHDL & Verilog HDL Designs for Use with MAX+PLUSÂ II Software
You can create VHDL and Verilog HDL design files with the MAX+PLUS® II Text Editor or another standard text editor and save them in the appropriate directory for your project.
The MAX+PLUSÂ II Text Editor offers the following advantages:
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Templates are available with the VHDL Templates and Verilog Templates commands (Template menu). These templates are also available in the ASCII vhdl.tmp and verilog.tmp files, respectively, which are located in the /usr/maxplus2 directory.
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If you use the MAX+PLUSÂ II Text Editor to create your VHDL design, you can turn on the Syntax Coloring command (Options menu). The Syntax Coloring feature displays keywords and other elements of text in text files in different colors to distinguish them from other forms of syntax.
To create a VHDL or Verilog HDL design file for use with the MAX+PLUSÂ II software, go through the following steps:
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Enter a VHDL or Verilog HDL design in the MAX+PLUSÂ II Text Editor or another standard text editor and save it in your working directory.
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Enter primitives, macrofunctions, and megafunctions in your VHDL or Verilog HDL design from the Altera library.
The following topics describe special steps needed to instantiate LPM and clklock functions:
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You can instantiate MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUSÂ II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support. |
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(Optional) Use the QuickHDL software to functionally simulate the design file, as described in Performing a Functional Simulation with QuickHDL Software and Performing a Functional Simulation with QuickHDL Pro Software.
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Once you have created a VHDL or Verilog HDL design, you can generate an EDIF netlist file that can be imported into the MAX+PLUSÂ II software with either of the following methods:
Installing the AlteraÂprovided MAX+PLUSÂ II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the following sample VHDL design files:
- /usr/maxplus2/examples/mentor/example5/count4.vhd
- /usr/maxplus2/examples/mentor/example6/count8.vhd
- /usr/maxplus2/examples/mentor/example8/adder16.vhd
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Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
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