|You can create your own libraries of custom functions for use in Design Architect schematics and VHDL and Verilog HDL design files. You can use custom functions to incorporate an EDIF Input File (.edf), Text Design File (.tdf), or any other MAX+PLUS II-supported design file into a project. The MAX+PLUS II software uses the |
Design Architect Libraries
You can enter a Design Architect schematic with logic functions from these Altera-provided symbol libraries: ALTERA LPMLIB, ALTERA GENLIB, LSTTL BY TYPE, and LSTTL ALL PARTS. You can access these libraries by choosing Altera Libraries (Libraries menu) in the Design Architect software. For information on using library of parameterized modules (LPM) functions, see ALTERA LPMLIB Library below.
ALTERA GENLIB Library (Design Architect) & Altera (VHDL) Libraries
The ALTERA GENLIB symbol library (called the Altera library for VHDL) includes several MAX+PLUS II primitives for controlling design synthesis and fitting. It also includes four macrofunctions (
81mux) that are optimized for different Altera device families, and the
clklock phase-locked loop megafunction, which is supported for some FLEX
The following table shows the MAX+PLUS II-specific logic functions.
|Table 1. MAX+PLUS II-Specific Logic Functions|
||8-bit full adder||
||Logic cell buffer||
||8-bit magnitude comparator||
||Global input buffer||
||8-bit up/down counter||
||FLEX 6000, FLEX 8000, and FLEX 10K cascade buffer||
||FLEX 6000, FLEX 8000, and FLEX 10K carry buffer||
|D-type flipflop with Clock Enable|
- Logic function names that begin with a number must be preceded by "
a_" in VHDL designs. For example,
8faddmust be specified as
- If you want to use QuickHDL software, make sure you have updated your quickhdl.ini file, as described in step 7 of Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.
- For designs that are targeted for FLEX 6000 devices, you should use the
DFFEprimitive only if the design contains either a Clear or Preset signal, but not both. If your design contains both a Clear and a Preset signal, you must use the
|Choose Old-Style Macrofunctions, Primitives, or Megafunctions/LPM from the MAX+PLUS II Help menu for detailed information on these functions.|
The Alteraprovided ALTERA LPMLIB library, which is available for Design Architect schematics and VHDL designs, includes standard functions from the library of parameterized modules (LPM) 2.1.0, except the truth table, finite state machine, and pad functions. The LPM standard defines a set of parameterized modules (i.e., parameterized functions) and their corresponding representations in an EDIF netlist file. These logic functions allow you to create and functionally simulate an LPM-based design without targeting a specific device family. After the design is completed, you can target the design to any device family. The parameters you specify for each LPM function determine which simulation models are generated.
|Choose Megafunctions/LPM from the MAX+PLUS II Help menu for more information about LPM functions.|
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