The MAX+PLUS
Design Architect Schematics
In Design Architect schematics, you can assign a limited subset of these resource assignments by assigning properties to symbols. These properties are incorporated into the EDIF netlist file(s). The MAX+PLUS II software automatically converts assignment information from the EDIF Input File into the ACF format. For information on making MAX+PLUS II-compatible resource assignments, go to the following topics:
- Assigning Pins, Logic Cells & Chips
- Assigning Cliques
- Assigning Logic Options
- Modifying the Assignment & Configuration File with the setacf Utility
| After you compile a project, you can back-annotate pin assignments, as described in BackAnnotating MAX+PLUS II Pin Assignments to Design Architect Symbols. |
Installing the Alteraprovided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the sample Design Architect schematic file /usr/maxplus2/examples/mentor/example4/fa2, which includes resource assignments.
VHDL & Verilog HDL Design Files
For Verilog HDL- and VHDL-based designs, you must use the MAX+PLUS II software or the setacf utility to enter resource assignments. Go to Modifying the Assignment & Configuration File with the setacf Utility for more information.
Related Topics:
- Go to "Resource Assignments in EDIF Input Files" and "Assigning Resources in a Third-Party Design Editor" in MAX+PLUS II Help for more information on assignments or properties that can be assigned in Design Architect software. For information on entering assignments in MAX+PLUS II software with Assign menu commands or in an ACF, go to "resource assignments" or "ACF, format" in MAX+PLUS II Help using Search for Help on (Help menu).
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Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.

