You can use Mentor Graphics Design Architect software to help you instantiate library of parameterized modules (LPM) functions in your VHDL design files.
To incorporate an LPM function into a VHDL design file, perform the following steps:
-
Be sure to set up the Design Architect working environment correctly, as described in Setting Up the MAX+PLUSÂ II/Mentor Graphics/Exemplar Logic Working Environment.
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Open a dummy schematic in the Design Architect software:
- Start the
Altera® /Mentor Graphics interface by typingmax2_dmgr
at a UNIX prompt. -
Start the Design Architect software by double-clicking Button 1 on the max2_da icon in the Design Manager tools window.
-
Choose the OPEN_SHEET button in the Design Architect session_palette, then specify your project name in the Component Name box. Choose OK.
- Start the
-
Instantiate the desired LPM function in the dummy schematic:
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Choose Altera Libraries (Library menu).
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Choose ALTERA LPMLIB (Altera Libraries menu).
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Choose from the available LPM functions on the ALTERA LPMLIB menu.
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In the LPM_<lpm function> dialog box, specify a name for the LPM function in the Cell Name box and appropriate values for the function's parameters. Make sure that any hexadecimal (Intel-format) file that you use to specify the initial content of a memory function does not have the same name as the design file name. Choose Megafunctions/LPM from the
MAX+PLUS®  II Help menu for detailed information about LPM functions. -
Choose OK to generate the LPM function, the corresponding VHDL simulation model, and a VHDL Component Declaration/Attribute Declaration/Attribute Specification (.cmp) template.
-
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Close the Design Architect software without saving the dummy schematic.
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Instantiate the function created in step 2 in your design file. Use the template file to help prevent syntax and other errors.
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Continue with the steps necessary to complete your design file, as described in Creating VHDL & Verilog HDL Designs for Use with MAX+PLUS
®  II Software.
Installing the AlteraÂprovided MAX+PLUSÂ II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the sample hierarchical VHDL design file /usr/maxplus2/examples/mentor/example8/adder16.vhd, which includes LPM function instantiation.
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Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
