Performing a Timing Simulation with QuickHDL Software
After you have entered a VHDL or Verilog HDL design file and compiled it with the MAX+PLUS® II Compiler, you can use Mentor Graphics QuickHDL software to simulate the MAX+PLUS IIgenerated VHDL Output File (.vhd) or Verilog Output File (.vo) and the Standard Delay Format (SDF) Output File (.sdo).
To simulate your VHDL or Verilog HDL design, go through the following steps:
Be sure to set up the working environment correctly, as described in Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment. Generate a VHDL or Verilog HDL output file and an SDF output file for your project, as described in Compiling Projects with MAX+PLUS II Software. Change to your project's directory. Copy your quickhdl.ini file to the same directory as your VHDL or Verilog HDL file. Type the following sets of commands at the UNIX prompt to create the work library and compile your project's VHDL or Verilog HDL output file:
| VHDL: |
Verilog HDL: |
setenv MGC_WD 'pwd' 
qhlib work
qvhcom <project name>.vho
|
setenv MGC_WD 'pwd'
qhlib work
qvlcom <project name>.vo
|
Type qhsim -sdftyp <project name>.sdo at the UNIX prompt to perform timing back-annotation and simulation and to display the QuickHDL simulation window.
If your Verilog HDL design uses memory functions (RAM or ROM) that can be initialized with a hexadecimal file (Intel-format) initialization, you must convert these files into Verilog HDL format using the Programming Language Interface (PLI). To use the Altera-provided source code for PLI, perform the following steps:
Download the file http://www.edif.org/lpmweb/convert_hex2ver.c to your project directory. Copy the following two files from the $MGC_HOME/shared/pkgs/quickhdl/include directory into the /usr/maxplus2 directory:
- $MGC_HOME/shared/pkgs/quickhdl/include/veriuser
- $MGC_HOME/shared/pkgs/quickhdl/include/acc_user
Refer to the Mentor Graphics QuickHDL User's Reference Manual, version 8.5-4.6i, for information on compiling the PLI application on different platforms and using the
Verilog HDL PLI.
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