Design Compiler & FPGA Compiler Technology Libraries
The Altera®-provided Design Compiler and FPGA Compiler technology libraries contain primitives that the Synopsys compilers use to map your designs to the target device architecture. These primitives contain timing and area information that the Synopsys compilers use to meet area and performance requirements. Table 1 shows the functions provided in these libraries. Choose Primitives from the MAX+PLUS II Help menu for detailed information on these functions.
Altera recommends instantiating these functions directly in your designs only if the Synopsys compilers do not appear to recognize the functions when synthesizing your design, or if you prefer to hand-optimize certain portions of your design.
| Table 1. Altera-Provided Primitives |
Name
Note (1),
Note (2) |
Description |
Name |
Description |
LCELL |
Logic cell buffer primitive |
EXP |
MAX® 5000, MAX 7000, and MAX 9000 Expander buffer primitive |
GLOBAL |
Global input buffer primitive |
SOFT |
Soft buffer primitive |
CASCADE |
FLEX® 6000, FLEX 8000, and FLEX 10K cascade buffer primitive |
OPNDRN |
FLEX 6000, FLEX 8000, and FLEX 10K Open-drain buffer primitive |
CARRY |
FLEX 6000, FLEX 8000, and FLEX 10K cascade buffer primitive |
DFF
DFFE
DFFS
Note (2) |
D-type flipflop with Clock Enable primitive |
LATCH |
Latch primitive |
TFF
TFFE
TFFS
Note (2) |
T-type flipflop primitive |
TRIBUF |
Tri-state buffer primitive |
|
|
| Notes: |
(1) All buffer primitive names except OPNDRN must be prefixed with an "A" in FLEX 6000, FLEX 8000, and FLEX 10K designs. The TRIBUF primitive is equivalent to the TRI primitive in the MAX+PLUS II software. |
(2) The DFFE and TFFE primitives include a Clock Enable input; the DFFS and TFFS primitives are equivalent to DFF and TFF primitives without Clear or Preset inputs. For designs that are targeted to FLEX 6000 devices, you should use the DFFE or TFFE primitive only if the design contains either a Clear or Preset signal, but not both. If your design contains both a Clear and a Preset signal, you must use the DFFE6K primitive. |
 |
The VHDL simulation model /usr/maxplus2/synopsys/library/alt_pre/<device
family>/src/<device
family>_components.vhd
file shows the exact cell and pin names for each device family.
The Verilog HDL simulation file /usr/maxplus2/synopsys/library/alt_pre/verilog/src/altera.v
shows the functionality of these cells.
|
Table 2 lists the technology library names.
| Table 2. Altera Technology Libraries |
| Altera Device Family | Synopsys Design Compiler | Synopsys FPGA Compiler |
| FLEX® 10K devices | flex10k.db
flex10k-2.db
flex10k-3.db
flex10k-4.db
flex10k-5.db | flex10k_fpga.db
flex10k-2_fpga.db
flex10k-3_fpga.db
flex10k-4_fpga.db
flex10k-5_fpga.db |
| FLEX 8000 devices | flex8000.db
flex8000-2.db
flex8000-3.db
flex8000-4.db
flex8000-5.db
flex8000-6.db | flex8000_fpga.db
flex8000-2_fpga.db
flex8000-3_fpga.db
flex8000-4_fpga.db
flex8000-5_fpga.db
flex8000-6_fpga.db |
| FLEX 6000 devices | flex6000-2.db
flex6000-3.db | flex6000-2_fpga.db
flex6000-3_fpga.db |
| MAX® 9000 devices | max9000.db | max9000_fpga.db |
MAX 7000, MAX 7000E,
MAX 7000S, & MAX 7000A devices | max7000.db | max7000_fpga.db |
| MAX 5000 & Classic® devices | max5000.db | max5000_fpga.db |
Related Links:
Feedback
Did this information help you?
If no, please log onto mySupport to file a technical request or enhancement.
Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.
|
Literature
> 
