You can create VHDL design files with the
- The MAX+PLUS II Text Editor offers VHDL templates with the VHDL Templates command (Templates menu) and syntax coloring with the Syntax Coloring command (Options menu).
- The FPGA Express internal text editor provides automatic error location when you double-click an error in the Output window.
To create a VHDL design that can be synthesized and optimized with the FPGA Express software, follow these steps:
- Describe your design using FPGA Express-supported VHDL constructs. For information on synthesizable VHDL constructs, refer to the online VHDL Reference Manual provided with the FPGA Express software. The following topics describe how to instantiate additional Altera-specific logic functions in your design:
- Instantiating the clklock Megafunction in VHDL or Verilog HDL
- Instantiating RAM & ROM Functions in VHDL
- Instantiating LPM Functions in VHDL

You can instantiate MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support. - Once you have created a design, synthesize and optimize it, as described in Synthesizing & Optimizing VHDL or Verilog HDL Files with FPGA Express Software.
Related Links:
- Go to the following MAX+PLUS II ACCESSSM Key topics for related information:
- Go to the following topics for additional information:
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